From patchwork Thu Oct 6 12:02:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 678865 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sqWnc0HT8z9s5w for ; Thu, 6 Oct 2016 23:15:32 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b=lL0TMiCR; dkim-atps=neutral Received: from localhost ([::1]:55340 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bs7aC-0006nj-8D for incoming@patchwork.ozlabs.org; Thu, 06 Oct 2016 08:15:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45867) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bs7Oc-0004PU-3X for qemu-devel@nongnu.org; Thu, 06 Oct 2016 08:03:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bs7OZ-0007Vf-Ae for qemu-devel@nongnu.org; Thu, 06 Oct 2016 08:03:29 -0400 Received: from ozlabs.org ([103.22.144.67]:49611) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bs7OZ-0007UW-00; Thu, 06 Oct 2016 08:03:27 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3sqWWb6V74z9t0P; Thu, 6 Oct 2016 23:03:23 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1475755403; bh=scjZNsSxNPvjbdedvvOt633f5BrUuN6KHRA0Fw8f40Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lL0TMiCRE2cjJdfOQv/zciW0zZWvN4a5mI4hZYVrHGFNbdofGduXl2Yv02tl0uZ5U 2XDs2NHlFnekhWE3cly/5StqG+untNEzeH2EEatepEU5IG3Zy/CRnxstX38TK1DpSx RMoOQ6kgb/G5AWd3bXVnTmXYJNWH2UwmsHfDgHCs= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 6 Oct 2016 23:02:55 +1100 Message-Id: <1475755395-27307-10-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1475755395-27307-1-git-send-email-david@gibson.dropbear.id.au> References: <1475755395-27307-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 09/29] target-ppc: improve lxvw4x implementation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, agraf@suse.de, Nikunj A Dadhania , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Nikunj A Dadhania Load 8byte at a time and manipulate. Big-Endian Storage +-------------+-------------+-------------+-------------+ | 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF | +-------------+-------------+-------------+-------------+ Little-Endian Storage +-------------+-------------+-------------+-------------+ | 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC | +-------------+-------------+-------------+-------------+ Vector load results in (32-bit elements): +----------+----------+----------+----------+ | 00112233 | 44556677 | 8899AABB | CCDDEEFF | +----------+----------+----------+----------+ Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson [dwg: Slight tweak to commit description] Signed-off-by: David Gibson --- target-ppc/translate/vsx-impl.inc.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c index c4c50dd..ec871b2 100644 --- a/target-ppc/translate/vsx-impl.inc.c +++ b/target-ppc/translate/vsx-impl.inc.c @@ -75,7 +75,6 @@ static void gen_lxvdsx(DisasContext *ctx) static void gen_lxvw4x(DisasContext *ctx) { TCGv EA; - TCGv_i64 tmp; TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); if (unlikely(!ctx->vsx_enabled)) { @@ -84,22 +83,27 @@ static void gen_lxvw4x(DisasContext *ctx) } gen_set_access_type(ctx, ACCESS_INT); EA = tcg_temp_new(); - tmp = tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); - gen_qemu_ld32u_i64(ctx, tmp, EA); - tcg_gen_addi_tl(EA, EA, 4); - gen_qemu_ld32u_i64(ctx, xth, EA); - tcg_gen_deposit_i64(xth, xth, tmp, 32, 32); - - tcg_gen_addi_tl(EA, EA, 4); - gen_qemu_ld32u_i64(ctx, tmp, EA); - tcg_gen_addi_tl(EA, EA, 4); - gen_qemu_ld32u_i64(ctx, xtl, EA); - tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32); - + if (ctx->le_mode) { + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ); + tcg_gen_shri_i64(t1, t0, 32); + tcg_gen_deposit_i64(xth, t1, t0, 32, 32); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ); + tcg_gen_shri_i64(t1, t0, 32); + tcg_gen_deposit_i64(xtl, t1, t0, 32, 32); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + } else { + tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); + } tcg_temp_free(EA); - tcg_temp_free_i64(tmp); } #define VSX_STORE_SCALAR(name, operation) \