From patchwork Sat Oct 1 10:05:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artyom Tarasenko X-Patchwork-Id: 677310 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3smPXy6jRBz9s3s for ; Sat, 1 Oct 2016 20:23:46 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=PMX7Bneh; dkim-atps=neutral Received: from localhost ([::1]:54998 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bqHSJ-00037E-QW for incoming@patchwork.ozlabs.org; Sat, 01 Oct 2016 06:23:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44249) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bqHCp-0006ai-Qp for qemu-devel@nongnu.org; Sat, 01 Oct 2016 06:07:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bqHCn-0007rq-Jd for qemu-devel@nongnu.org; Sat, 01 Oct 2016 06:07:42 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:32860) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bqHCn-0007rY-94 for qemu-devel@nongnu.org; Sat, 01 Oct 2016 06:07:41 -0400 Received: by mail-wm0-x241.google.com with SMTP id p138so6759228wmb.0 for ; Sat, 01 Oct 2016 03:07:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dx+2C8Q+Q6gRsDFKZ2CHS1stRh3fEv6idaJpE1sQE+I=; b=PMX7BnehTn64YiH/r/RbcyHitjtt2mhfDK7IUjil3obxTKFJomfiOGc9+PWF/dBmTs Qpmd1hsW5Lzd2UQt3jlynBppdvsUFFHnYIEnf9M0gJjE+In+zxal3v4KVDZjIEZ5ciiq BghXNtqSqu/8rkRkkx89S09ou6MdN8IrkGtTgxBFfxbrN232xtuVPnKnem9iTEpMawWf dw0rWPu2eCe6PIycFiflbtZxA7GeKbCyWl9hKSxWrAb2gIjQTmf7fgGsaUQmW9BvQK0O KL/EXMHtNS/a3vE/Zm4lTG72nxoAS89+gT2/shepq3iYpn6TlsOYBhp6wEeed4IqVThT J9SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dx+2C8Q+Q6gRsDFKZ2CHS1stRh3fEv6idaJpE1sQE+I=; b=T22ebh739YBm4+V/I2XtCOkKKEDqg9Zw52NkoXDjuVbxoYlNaq2k/MT6xN2e/U/nvE 9paS2YstG6r00FLZeYdEgG7LuuVHaaoMimpxMNZeW2QG7I6T3E9Qe0yju2VsJ+UafwN1 iX+e/Pz9oZG8RNSeuL21/7xqKBYsh5ne2JUBK9Dpa47T8WdFSrFvZOXGf66onVd+dv+v J8JlHVaa/m0s2i00E+AutwFkR4cJQoIcQ7aNigq8U0uQnSeOMB6fidCfP8fLeQP9d0+b 4Y3UwhX9z6hioN2tK1tQ3WTKTuUwaCoOOsdvAWQsB79C0sc44RTralqL9ncyjcbI/zng ZaTw== X-Gm-Message-State: AA6/9RmZ4w2aLjfoMfInS9KPGij0SB1CHWZfUBDE2KMV2pG+95NFpRGh45sR7C5Y82VfgQ== X-Received: by 10.28.174.76 with SMTP id x73mr1689521wme.60.1475316460586; Sat, 01 Oct 2016 03:07:40 -0700 (PDT) Received: from localhost (x55b4da19.dyn.telefonica.de. [85.180.218.25]) by smtp.gmail.com with ESMTPSA id bc5sm23909093wjb.37.2016.10.01.03.07.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 01 Oct 2016 03:07:39 -0700 (PDT) From: Artyom Tarasenko To: qemu-devel@nongnu.org Date: Sat, 1 Oct 2016 12:05:27 +0200 Message-Id: <1475316333-9776-24-git-send-email-atar4qemu@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1475316333-9776-1-git-send-email-atar4qemu@gmail.com> References: <1475316333-9776-1-git-send-email-atar4qemu@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH 23/29] target-sparc: implement ST_BLKINIT_ ASIs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In OpenSPARC T1+ TWINX ASIs in store instructions are aliased with Block Initializing Store ASIs. "UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them in the chapter "5.9 Block Initializing Store ASIs" Integer stores of all sizes are allowed with these ASIs. Signed-off-by: Artyom Tarasenko --- target-sparc/ldst_helper.c | 22 +++++++++++----------- target-sparc/translate.c | 17 ++++++++++++++--- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index c27e668..f59293d 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -1766,6 +1766,9 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ case ASI_PL: /* Primary LE */ case ASI_SL: /* Secondary LE */ + case ASI_TWINX_AIUS_L: /* 0x2b, ASI_STBI_AIUS_L */ + case ASI_TWINX_PL: /* 0xea ASI_ST_BLKINIT_PRIMARY_LITTLE */ + case ASI_TWINX_SL: /* 0xeb ASI_ST_BLKINIT_SECONDARY_LITTLE */ switch (size) { case 2: val = bswap16(val); @@ -1784,6 +1787,14 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, } switch (asi) { + case ASI_TWINX_AIUP: /* 0x22 ASI_STBI_AIUP */ + case ASI_TWINX_AIUP_L: /* 0x2a ASI_STBI_AIUPL_L */ + case ASI_TWINX_AIUS: /* 0x23 ASI_STBI_AIUS */ + case ASI_TWINX_AIUS_L: /* 0x2b ASI_STBI_AIUS_L */ + case ASI_BLK_INIT_QUAD_LDD_P: /* 0xe2 Primary block init */ + case ASI_BLK_INIT_QUAD_LDD_S: /* 0xe3 Secondary block init */ + case ASI_TWINX_PL: /* 0xea ASI_ST_BLKINIT_PRIMARY_LITTLE */ + case ASI_TWINX_SL: /* 0xeb ASI_ST_BLKINIT_SECONDARY_LITTLE */ case ASI_AIUP: /* As if user primary */ case ASI_AIUS: /* As if user secondary */ case ASI_AIUPL: /* As if user primary LE */ @@ -2154,19 +2165,8 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, return; case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ - case ASI_TWINX_AIUP: /* As if user primary, twinx */ - case ASI_TWINX_AIUS: /* As if user secondary, twinx */ case ASI_TWINX_REAL: /* Real address, twinx */ - case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ - case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ - case ASI_TWINX_N: /* Nucleus, twinx */ - case ASI_TWINX_NL: /* Nucleus, twinx, LE */ - /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ - case ASI_TWINX_P: /* Primary, twinx */ - case ASI_TWINX_PL: /* Primary, twinx, LE */ - case ASI_TWINX_S: /* Secondary, twinx */ - case ASI_TWINX_SL: /* Secondary, twinx, LE */ /* Only stda allowed */ helper_raise_exception(env, TT_ILL_INSN); return; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 6520bb3..c7fbcbc 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2234,13 +2234,24 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, switch (da.type) { case GET_ASI_EXCP: break; - case GET_ASI_DTWINX: /* Reserved for stda. */ - gen_exception(dc, TT_ILL_INSN); - break; case GET_ASI_DIRECT: gen_address_mask(dc, addr); tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop); break; + case GET_ASI_DTWINX: +#ifndef TARGET_SPARC64 + gen_exception(dc, TT_ILL_INSN); + break; +#else + if (!(dc->def->features & CPU_FEATURE_HYPV)) { + /* Pre OpenSPARC CPUs don't have these */ + gen_exception(dc, TT_ILL_INSN); + return; + } + /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions + * are ST_BLKINIT_ ASIs */ + /* fall through */ +#endif default: { TCGv_i32 r_asi = tcg_const_i32(da.asi);