From patchwork Fri Sep 30 18:49:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Habkost X-Patchwork-Id: 677180 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sm13T5fYkz9s3s for ; Sat, 1 Oct 2016 05:00:21 +1000 (AEST) Received: from localhost ([::1]:46435 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bq32g-0003wj-GX for incoming@patchwork.ozlabs.org; Fri, 30 Sep 2016 15:00:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43749) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bq2t4-0002wO-W9 for qemu-devel@nongnu.org; Fri, 30 Sep 2016 14:50:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bq2t3-0003G6-3b for qemu-devel@nongnu.org; Fri, 30 Sep 2016 14:50:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44700) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bq2t2-0003Fj-Tg for qemu-devel@nongnu.org; Fri, 30 Sep 2016 14:50:21 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5CA99B4C4B; Fri, 30 Sep 2016 18:50:20 +0000 (UTC) Received: from localhost (ovpn-116-132.phx2.redhat.com [10.3.116.132]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u8UIoJYO032127; Fri, 30 Sep 2016 14:50:19 -0400 From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Fri, 30 Sep 2016 15:49:42 -0300 Message-Id: <1475261386-20211-9-git-send-email-ehabkost@redhat.com> In-Reply-To: <1475261386-20211-1-git-send-email-ehabkost@redhat.com> References: <1475261386-20211-1-git-send-email-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Fri, 30 Sep 2016 18:50:20 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v5 08/12] target-i386: xsave: Add FP and SSE bits to x86_ext_save_areas X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: libvir-list@redhat.com, Markus Armbruster , dahi@linux.vnet.ibm.com, Paolo Bonzini , Igor Mammedov , Jiri Denemark , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Instead of treating the FP and SSE bits as special cases, add them to the x86_ext_save_areas array. This will simplify the code that calculates the supported xsave components and the size of the xsave area. Signed-off-by: Eduardo Habkost --- Changes series v3 -> v4: * New patch added to series --- target-i386/cpu.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index c018122..477990d 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -535,6 +535,20 @@ typedef struct ExtSaveArea { } ExtSaveArea; static const ExtSaveArea x86_ext_save_areas[] = { + [XSTATE_FP_BIT] = { + /* x87 FP state component is always enabled if XSAVE is supported */ + .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, + /* x87 state is in the legacy region of the XSAVE area */ + .offset = 0, + .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), + }, + [XSTATE_SSE_BIT] = { + /* SSE state component is always enabled if XSAVE is supported */ + .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, + /* SSE state is in the legacy region of the XSAVE area */ + .offset = 0, + .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), + }, [XSTATE_YMM_BIT] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, .offset = offsetof(X86XSaveArea, avx_state), @@ -568,9 +582,9 @@ static const ExtSaveArea x86_ext_save_areas[] = { static uint32_t xsave_area_size(uint64_t mask) { int i; - uint64_t ret = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader); + uint64_t ret = 0; - for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { + for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa = &x86_ext_save_areas[i]; if ((mask >> i) & 1) { ret = MAX(ret, esa->offset + esa->size); @@ -2961,8 +2975,8 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu) return; } - mask = (XSTATE_FP_MASK | XSTATE_SSE_MASK); - for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { + mask = 0; + for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa = &x86_ext_save_areas[i]; if (env->features[esa->feature] & esa->bits) { mask |= (1ULL << i);