diff mbox

[v4,2/9] target-ppc: Implement mtvsrdd instruction

Message ID 1475040687-27523-3-git-send-email-nikunj@linux.vnet.ibm.com
State New
Headers show

Commit Message

Nikunj A Dadhania Sept. 28, 2016, 5:31 a.m. UTC 
From: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>

mtvsrdd: Move To VSR Double Doubleword

Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/translate/vsx-impl.inc.c | 23 +++++++++++++++++++++++
 target-ppc/translate/vsx-ops.inc.c  |  1 +
 2 files changed, 24 insertions(+)

Comments

Richard Henderson Sept. 28, 2016, 4:01 p.m. UTC | #1 
On 09/27/2016 10:31 PM, Nikunj A Dadhania wrote:
> +    if (!rA(ctx->opcode)) {
> +        tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0);
> +    } else {
> +       tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]);
> +    }

Indentation.  Otherwise,

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
Nikunj A Dadhania Sept. 28, 2016, 5:06 p.m. UTC | #2 
Richard Henderson <rth@twiddle.net> writes:

> On 09/27/2016 10:31 PM, Nikunj A Dadhania wrote:
>> +    if (!rA(ctx->opcode)) {
>> +        tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0);
>> +    } else {
>> +       tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]);
>> +    }
>
> Indentation.  Otherwise,

Sure, not sure how it escaped check-patch.

Regards
Nikunj
David Gibson Sept. 29, 2016, 1:29 a.m. UTC | #3 
On Wed, Sep 28, 2016 at 11:01:20AM +0530, Nikunj A Dadhania wrote:
> From: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
> 
> mtvsrdd: Move To VSR Double Doubleword
> 
> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
>  target-ppc/translate/vsx-impl.inc.c | 23 +++++++++++++++++++++++
>  target-ppc/translate/vsx-ops.inc.c  |  1 +
>  2 files changed, 24 insertions(+)
> 
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index b669e8c..f9db1d4 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -234,6 +234,29 @@ static void gen_mfvsrld(DisasContext *ctx)
>      tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_vsrl(xS(ctx->opcode)));
>  }
>  
> +static void gen_mtvsrdd(DisasContext *ctx)
> +{
> +    if (xT(ctx->opcode) < 32) {
> +        if (unlikely(!ctx->vsx_enabled)) {
> +            gen_exception(ctx, POWERPC_EXCP_VSXU);
> +            return;
> +        }
> +    } else {
> +        if (unlikely(!ctx->altivec_enabled)) {
> +            gen_exception(ctx, POWERPC_EXCP_VPU);
> +            return;
> +        }
> +    }

Huh.. so in the ISA doc version I have at least (p114), the
pseudo-code for the instruction states either vector or VSX
exceptions.  The text however says either FP or vector exceptions.

The pseudo-code version seems more sensible which is what you've
implemented, so I'm guessing this is just an error in the descriptive
text.

It'd be nice to confirm that against real hardware behaviour if
possible though.

> +
> +    if (!rA(ctx->opcode)) {
> +        tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0);
> +    } else {
> +       tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]);
> +    }
> +
> +    tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rB(ctx->opcode)]);
> +}
> +
>  #endif
>  
>  static void gen_xxpermdi(DisasContext *ctx)
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index 3b296f8..1287973 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -23,6 +23,7 @@ GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
>  GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
>  GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
>  GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
> +GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
>  #endif
>  
>  #define GEN_XX1FORM(name, opc2, opc3, fl2)                              \
Nikunj A Dadhania Sept. 29, 2016, 3:20 a.m. UTC | #4 
David Gibson <david@gibson.dropbear.id.au> writes:

> [ Unknown signature status ]
> On Wed, Sep 28, 2016 at 11:01:20AM +0530, Nikunj A Dadhania wrote:
>> From: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
>> 
>> mtvsrdd: Move To VSR Double Doubleword
>> 
>> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>>  target-ppc/translate/vsx-impl.inc.c | 23 +++++++++++++++++++++++
>>  target-ppc/translate/vsx-ops.inc.c  |  1 +
>>  2 files changed, 24 insertions(+)
>> 
>> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
>> index b669e8c..f9db1d4 100644
>> --- a/target-ppc/translate/vsx-impl.inc.c
>> +++ b/target-ppc/translate/vsx-impl.inc.c
>> @@ -234,6 +234,29 @@ static void gen_mfvsrld(DisasContext *ctx)
>>      tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_vsrl(xS(ctx->opcode)));
>>  }
>>  
>> +static void gen_mtvsrdd(DisasContext *ctx)
>> +{
>> +    if (xT(ctx->opcode) < 32) {
>> +        if (unlikely(!ctx->vsx_enabled)) {
>> +            gen_exception(ctx, POWERPC_EXCP_VSXU);
>> +            return;
>> +        }
>> +    } else {
>> +        if (unlikely(!ctx->altivec_enabled)) {
>> +            gen_exception(ctx, POWERPC_EXCP_VPU);
>> +            return;
>> +        }
>> +    }
>
> Huh.. so in the ISA doc version I have at least (p114), the
> pseudo-code for the instruction states either vector or VSX
> exceptions.  The text however says either FP or vector exceptions.
>
> The pseudo-code version seems more sensible which is what you've
> implemented, so I'm guessing this is just an error in the descriptive
> text.

Right.

> It'd be nice to confirm that against real hardware behaviour if
> possible though.

Sure, will check it.

Regards,
Nikunj
diff mbox

Patch

diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index b669e8c..f9db1d4 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -234,6 +234,29 @@  static void gen_mfvsrld(DisasContext *ctx)
     tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_vsrl(xS(ctx->opcode)));
 }
 
+static void gen_mtvsrdd(DisasContext *ctx)
+{
+    if (xT(ctx->opcode) < 32) {
+        if (unlikely(!ctx->vsx_enabled)) {
+            gen_exception(ctx, POWERPC_EXCP_VSXU);
+            return;
+        }
+    } else {
+        if (unlikely(!ctx->altivec_enabled)) {
+            gen_exception(ctx, POWERPC_EXCP_VPU);
+            return;
+        }
+    }
+
+    if (!rA(ctx->opcode)) {
+        tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0);
+    } else {
+       tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]);
+    }
+
+    tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rB(ctx->opcode)]);
+}
+
 #endif
 
 static void gen_xxpermdi(DisasContext *ctx)
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 3b296f8..1287973 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -23,6 +23,7 @@  GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
 #endif
 
 #define GEN_XX1FORM(name, opc2, opc3, fl2)                              \