From patchwork Thu Sep 22 17:21:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 673626 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sg4wh5dJ1z9s65 for ; Fri, 23 Sep 2016 04:37:24 +1000 (AEST) Received: from localhost ([::1]:56552 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bn8s6-0007Ur-Bi for incoming@patchwork.ozlabs.org; Thu, 22 Sep 2016 14:37:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37469) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bn7ha-0005gI-Pp for qemu-devel@nongnu.org; Thu, 22 Sep 2016 13:22:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bn7hY-0002dA-Bm for qemu-devel@nongnu.org; Thu, 22 Sep 2016 13:22:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47093) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bn7hY-0002ce-5H for qemu-devel@nongnu.org; Thu, 22 Sep 2016 13:22:24 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1bn7hX-0007G1-Ks for qemu-devel@nongnu.org; Thu, 22 Sep 2016 18:22:23 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 22 Sep 2016 18:21:53 +0100 Message-Id: <1474564935-23831-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1474564935-23831-1-git-send-email-peter.maydell@linaro.org> References: <1474564935-23831-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/36] aspeed: add a ram_size property to the memory controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Configure the size of the RAM of the SOC using a property to propagate the value down to the memory controller from the board level. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Message-id: 1473438177-26079-14-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 2 ++ hw/arm/aspeed_soc.c | 2 ++ hw/misc/aspeed_sdmc.c | 23 +++++++++++++---------- include/hw/misc/aspeed_sdmc.h | 1 + 4 files changed, 18 insertions(+), 10 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 9013d35..562bbb2 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -113,6 +113,8 @@ static void aspeed_board_init(MachineState *machine, &bmc->ram); object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram), &error_abort); + object_property_set_int(OBJECT(&bmc->soc), ram_size, "ram-size", + &error_abort); object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", &error_abort); object_property_set_bool(OBJECT(&bmc->soc), true, "realized", diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 93bc7bb..c0a3102 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -113,6 +113,8 @@ static void aspeed_soc_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default()); qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev", sc->info->silicon_rev); + object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), + "ram-size", &error_abort); } static void aspeed_soc_realize(DeviceState *dev, Error **errp) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 20bcdb5..8830dc0 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -140,9 +140,9 @@ static const MemoryRegionOps aspeed_sdmc_ops = { .valid.max_access_size = 4, }; -static int ast2400_rambits(void) +static int ast2400_rambits(AspeedSDMCState *s) { - switch (ram_size >> 20) { + switch (s->ram_size >> 20) { case 64: return ASPEED_SDMC_DRAM_64MB; case 128: @@ -156,14 +156,15 @@ static int ast2400_rambits(void) } /* use a common default */ - error_report("warning: Invalid RAM size 0x" RAM_ADDR_FMT - ". Using default 256M", ram_size); + error_report("warning: Invalid RAM size 0x%" PRIx64 + ". Using default 256M", s->ram_size); + s->ram_size = 256 << 20; return ASPEED_SDMC_DRAM_256MB; } -static int ast2500_rambits(void) +static int ast2500_rambits(AspeedSDMCState *s) { - switch (ram_size >> 20) { + switch (s->ram_size >> 20) { case 128: return ASPEED_SDMC_AST2500_128MB; case 256: @@ -177,8 +178,9 @@ static int ast2500_rambits(void) } /* use a common default */ - error_report("warning: Invalid RAM size 0x" RAM_ADDR_FMT - ". Using default 512M", ram_size); + error_report("warning: Invalid RAM size 0x%" PRIx64 + ". Using default 512M", s->ram_size); + s->ram_size = 512 << 20; return ASPEED_SDMC_AST2500_512MB; } @@ -222,11 +224,11 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) switch (s->silicon_rev) { case AST2400_A0_SILICON_REV: - s->ram_bits = ast2400_rambits(); + s->ram_bits = ast2400_rambits(s); break; case AST2500_A0_SILICON_REV: case AST2500_A1_SILICON_REV: - s->ram_bits = ast2500_rambits(); + s->ram_bits = ast2500_rambits(s); break; default: g_assert_not_reached(); @@ -249,6 +251,7 @@ static const VMStateDescription vmstate_aspeed_sdmc = { static Property aspeed_sdmc_properties[] = { DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0), + DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h index df7dce0..551c8af 100644 --- a/include/hw/misc/aspeed_sdmc.h +++ b/include/hw/misc/aspeed_sdmc.h @@ -26,6 +26,7 @@ typedef struct AspeedSDMCState { uint32_t regs[ASPEED_SDMC_NR_REGS]; uint32_t silicon_rev; uint32_t ram_bits; + uint64_t ram_size; } AspeedSDMCState;