From patchwork Thu Sep 8 22:31:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Rolnik X-Patchwork-Id: 667810 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sVZrd1cLrz9s3T for ; Fri, 9 Sep 2016 08:34:25 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=k7k1Iwks; dkim-atps=neutral Received: from localhost ([::1]:54436 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi7tl-0004H4-So for incoming@patchwork.ozlabs.org; Thu, 08 Sep 2016 18:34:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi7sA-00035H-Ij for qemu-devel@nongnu.org; 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} +static void gen_sub_Cf(TCGv dest, TCGv src1, TCGv src2) +{ + TCGv t1 = tcg_temp_new_i32(); + TCGv t2 = tcg_temp_new_i32(); + TCGv t3 = tcg_temp_new_i32(); + + tcg_gen_not_tl(t1, src1); /* t1 = ~src1 */ + tcg_gen_and_tl(t2, t1, src2); /* t2 = ~src1 & src2 */ + tcg_gen_or_tl(t3, t1, src2); /* t3 = (~src1 | src2) & dest */ + tcg_gen_and_tl(t3, t3, dest); + tcg_gen_or_tl(t2, t2, t3); /* t2 = ~src1 & src2 + | ~src1 & dest + | dest & src2 */ + tcg_gen_shri_tl(cpu_Cf, t2, 31);/* Cf = t2(31) */ + + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t1); +} + +static void gen_sub_Vf(TCGv dest, TCGv src1, TCGv src2) +{ + TCGv t1 = tcg_temp_new_i32(); + TCGv t2 = tcg_temp_new_i32(); + + /* + t1 = src1 & ~src2 & ~dest + | ~src1 & src2 & dest + = (src1 ^ dest) & (src1 ^ dest)*/ + tcg_gen_xor_tl(t1, src1, dest); + tcg_gen_xor_tl(t2, src1, src2); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_shri_tl(cpu_Vf, t1, 31);/* Vf = t1(31) */ + + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t1); +} + /* ADC */ @@ -168,3 +206,130 @@ int arc_gen_ADD3(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) return BS_NONE; } +/* + SUB +*/ +int arc_gen_SUB(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv rslt = dest; + + if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_sub_tl(rslt, src1, src2); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + gen_sub_Cf(rslt, src1, src2); + gen_sub_Vf(rslt, src1, src2); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + + return BS_NONE; +} + +/* + SBC +*/ +int arc_gen_SBC(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv rslt = dest; + + if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_sub_tl(rslt, src1, src2); + tcg_gen_sub_tl(rslt, rslt, cpu_Cf); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + gen_sub_Cf(rslt, src1, src2); + gen_sub_Vf(rslt, src1, src2); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + + return BS_NONE; +} +/* + SUB1 +*/ +int arc_gen_SUB1(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv t0 = tcg_temp_new_i32(); + + tcg_gen_shli_tl(t0, src2, 1); + arc_gen_SUB(ctx, dest, src1, t0); + + tcg_temp_free_i32(t0); + + return BS_NONE; +} + +/* + SUB2 +*/ +int arc_gen_SUB2(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv t0 = tcg_temp_new_i32(); + + tcg_gen_shli_tl(t0, src2, 2); + arc_gen_SUB(ctx, dest, src1, t0); + + tcg_temp_free_i32(t0); + + return BS_NONE; +} + +/* + SUB3 +*/ +int arc_gen_SUB3(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv t0 = tcg_temp_new_i32(); + + tcg_gen_shli_tl(t0, src2, 3); + arc_gen_SUB(ctx, dest, src1, t0); + + tcg_temp_free_i32(t0); + + return BS_NONE; +} + +/* + RSUB +*/ +int arc_gen_RSUB(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + return arc_gen_SUB(ctx, dest, src2, src1); +} + +/* + CMP +*/ +int arc_gen_CMP(DisasCtxt *ctx, TCGv src1, TCGv src2) +{ + TCGv rslt = tcg_temp_new_i32(); + + tcg_gen_sub_tl(rslt, src1, src2); + + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + gen_sub_Cf(rslt, src1, src2); + gen_sub_Vf(rslt, src1, src2); + + tcg_temp_free_i32(rslt); + + return BS_NONE; +} diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h index 08e23c7..40ed8a0 100644 --- a/target-arc/translate-inst.h +++ b/target-arc/translate-inst.h @@ -28,3 +28,11 @@ int arc_gen_ADD1(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); int arc_gen_ADD2(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); int arc_gen_ADD3(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_SUB(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_SUB1(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_SUB2(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_SUB3(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_SBC(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_RSUB(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_CMP(DisasCtxt *c, TCGv src1, TCGv src2); +