From patchwork Thu Sep 8 22:32:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Rolnik X-Patchwork-Id: 667828 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sVbFX1TKzz9rxv for ; Fri, 9 Sep 2016 08:52:32 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=BzHpJrUc; dkim-atps=neutral Received: from localhost ([::1]:54531 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi8BJ-0003rL-5b for incoming@patchwork.ozlabs.org; Thu, 08 Sep 2016 18:52:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44747) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi7sZ-0003Pj-I5 for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:33:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bi7sV-0000mz-BQ for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:33:06 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:32937) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi7sV-0000md-1D for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:33:03 -0400 Received: by mail-wm0-x242.google.com with SMTP id b187so209643wme.0 for ; Thu, 08 Sep 2016 15:33:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P+HWZ3d5JnBl1Xf9hjn72hbmTOSi3+48fSLEEOoYAGM=; b=BzHpJrUc+BbgBNubP80WbYFMdGJU6C88Dy7w8LjmqsdYPhd+al7sDZ2QH0p9D54sAW NiVR4FPDmAqkWiBUg58mcnVnwMl03tOsi1nhtMx1BmBvlO60tvQczGDtldQoEjAm8yH5 CVeaPhE56ncZTugdcHsOreRKwBih9Uas/DEA/i4rHI11Q6+GJLrwN6tAfPUlVXaoZ7Py Vtq9VkhzfTr36v36cgDrW7qiQNM4Pwkhs0x+uqZoenu2cs86OB+AvhxzW/dbFmMmkFbd DIMEqtgrhUxFbgegpJFU/8x1/VaQRZUj+nR9uC0KSKI4RlXYn3UdjYNjwsGl/mkhMpfJ okqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P+HWZ3d5JnBl1Xf9hjn72hbmTOSi3+48fSLEEOoYAGM=; b=Xr3n8f27qylAwDxBNz6z3KfUj9nBhEmjWWYm0suCTd4lM2+GG9GCT+6imWZgYbxOb1 gC1Z9gwD91mYYZbD+8S+drV6rUKL6SCDwr7d7NHfRgX2YhVDLONSK6uvNdcMLfkUt+Le W9gP9QTTHEW4y4ny0/DzH7NV13BJZyZlwgoLf0jE8pk4JX45R+R1heyTRge160Op+wgn DW3QlhU6rL6HZ/Jzc5Qw5AdpThuvE6PVHS9kLBO2FjcCe1bphXXw/9M6RXY+NGEMR+F0 W+iAL1tohYOAadchzcbqU5l6DVmvK2g14TUgOkyMhZ+5fhOBA6QREQ4Z+q/ucECL/+yu WFFg== X-Gm-Message-State: AE9vXwMqO/BIFJ3tvqsSNqm3ZS0TlKXDbsV3LMwLaYEvwWDDDIWw44eh/3FPsnnpyvtxMg== X-Received: by 10.28.54.6 with SMTP id d6mr647098wma.68.1473373982231; Thu, 08 Sep 2016 15:33:02 -0700 (PDT) Received: from a0999b0126e1.ant.amazon.com ([94.230.86.12]) by smtp.gmail.com with ESMTPSA id d8sm276298wmi.0.2016.09.08.15.33.00 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Sep 2016 15:33:01 -0700 (PDT) From: Michael Rolnik To: qemu-devel@nongnu.org Date: Fri, 9 Sep 2016 01:32:01 +0300 Message-Id: <1473373930-31547-21-git-send-email-mrolnik@gmail.com> X-Mailer: git-send-email 2.4.9 (Apple Git-60) In-Reply-To: <1473373930-31547-1-git-send-email-mrolnik@gmail.com> References: <1473373930-31547-1-git-send-email-mrolnik@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH RFC v1 20/29] target-arc: ADDS, ADDSDW, SUBS, SUBSDW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Rolnik Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Michael Rolnik --- target-arc/translate-inst.c | 227 ++++++++++++++++++++++++++++++++++++++++++++ target-arc/translate-inst.h | 4 + 2 files changed, 231 insertions(+) diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c index 603a0a8..d5c739e 100644 --- a/target-arc/translate-inst.c +++ b/target-arc/translate-inst.c @@ -271,6 +271,45 @@ void arc_gen_jump_ifnot(DisasCtxt *ctx, ARC_COND cond, TCGLabel *label_skip) gen_set_label(label_cont); } +static void gen_add16_Vf(TCGv v, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv t1 = tcg_temp_new_i32(); + TCGv t2 = tcg_temp_new_i32(); + + /* + + src1 & src2 & ~dest | ~src1 & ~src2 & dest = (src1 ^ dest) & ~(src1 ^ src2) + + */ + tcg_gen_xor_tl(t1, src1, dest); /* t1 = src1 ^ dest */ + tcg_gen_xor_tl(t2, src1, src2); /* t2 = src1 ^ src2 */ + tcg_gen_andc_tl(t1, t1, t2); /* t1 = (src1 ^ src2) & ~(src1 ^ src2) */ + + tcg_gen_shri_tl(v, t1, 15);/* Vf = t1(15) */ + + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t1); +} + + +static void gen_sub16_Vf(TCGv v, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv t1 = tcg_temp_new_i32(); + TCGv t2 = tcg_temp_new_i32(); + + /* + t1 = src1 & ~src2 & ~dest + | ~src1 & src2 & dest + = (src1 ^ dest) & (src1 ^ dest)*/ + tcg_gen_xor_tl(t1, src1, dest); + tcg_gen_xor_tl(t2, src1, src2); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_shri_tl(v, t1, 15); /* Vf = t1(15) */ + + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t1); +} + /* ADC */ @@ -2095,3 +2134,191 @@ int arc_gen_SR(DisasCtxt *ctx, TCGv src1, TCGv src2) return BS_NONE; } +/* + ADDS +*/ +int arc_gen_ADDS(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv rslt = dest; + TCGv t1 = tcg_temp_new_i32(); + TCGv t2 = tcg_temp_new_i32(); + TCGv sat = tcg_temp_new_i32(); + + if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_add_tl(rslt, src1, src2); + + /* + src1 & src2 & ~dest | ~src1 & ~src2 & dest + = (src1 ^ dest) & ~(src1 ^ src2) + */ + tcg_gen_xor_tl(t1, src1, rslt); /* t1 = src1 ^ dest */ + tcg_gen_xor_tl(t2, src1, src2); /* t2 = src1 ^ src2 */ + tcg_gen_andc_tl(t1, t1, t2); /* t1 = (src1 ^ src2) & ~(src1 ^ src2) */ + + tcg_gen_shri_tl(sat, t1, 31); /* sat= t1(31) */ + + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t1); + + tcg_gen_movcond_tl(TCG_COND_LTU, rslt, dest, ctx->msb32, dest, ctx->smax32); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_mov_tl(cpu_Cf, ctx->zero); + tcg_gen_mov_tl(cpu_Vf, sat); + tcg_gen_or_tl(cpu_S1f, cpu_S2f, sat); + tcg_gen_or_tl(cpu_S1f, cpu_S2f, sat); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + + return BS_NONE; +} + +/* + ADDSDW +*/ +int arc_gen_ADDSDW(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv rslt = dest; + TCGv loB = tcg_temp_new_i32(); + TCGv hiB = tcg_temp_new_i32(); + TCGv loC = tcg_temp_new_i32(); + TCGv hiC = tcg_temp_new_i32(); + TCGv loA = tcg_temp_new_i32(); + TCGv hiA = tcg_temp_new_i32(); + TCGv hiS = tcg_temp_new_i32(); + TCGv loS = tcg_temp_new_i32(); + + if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_andi_tl(loB, src1, 0xffff); + tcg_gen_shri_tl(hiB, src1, 16); + + tcg_gen_andi_tl(loC, src2, 0xffff); + tcg_gen_shri_tl(hiC, src2, 16); + + tcg_gen_add_tl(loA, loB, loC); + tcg_gen_add_tl(hiA, hiB, hiC); + + tcg_gen_movcond_tl(TCG_COND_LTU, loA, loA, ctx->msb16, loA, ctx->smax16); + tcg_gen_movcond_tl(TCG_COND_LTU, hiA, hiA, ctx->msb16, hiA, ctx->smax16); + + tcg_gen_deposit_tl(rslt, loA, hiA, 16, 16); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_movi_tl(cpu_Cf, 0); + + gen_add16_Vf(hiS, hiA, hiB, hiC); + gen_add16_Vf(loS, loA, loB, loC); + + tcg_gen_or_tl(cpu_Vf, hiS, loS); + tcg_gen_or_tl(cpu_S1f, cpu_S1f, hiS); + tcg_gen_or_tl(cpu_S2f, cpu_S2f, loS); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + tcg_temp_free_i32(loA); + tcg_temp_free_i32(hiA); + tcg_temp_free_i32(loB); + tcg_temp_free_i32(hiB); + tcg_temp_free_i32(loC); + tcg_temp_free_i32(hiC); + tcg_temp_free_i32(hiS); + tcg_temp_free_i32(loS); + + return BS_NONE; +} + +/* + SUBS +*/ +int arc_gen_SUBS(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv temp = tcg_temp_new_i32(); + + tcg_gen_mov_tl(temp, src2); + + arc_gen_ADDS(ctx, dest, src1, temp); + + tcg_temp_free_i32(temp); + + return BS_NONE; +} + +/* + SUBSDW +*/ +int arc_gen_SUBSDW(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv rslt = dest; + TCGv loB = tcg_temp_new_i32(); + TCGv hiB = tcg_temp_new_i32(); + TCGv loC = tcg_temp_new_i32(); + TCGv hiC = tcg_temp_new_i32(); + TCGv loA = tcg_temp_new_i32(); + TCGv hiA = tcg_temp_new_i32(); + TCGv hiS = tcg_temp_new_i32(); + TCGv loS = tcg_temp_new_i32(); + + if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_andi_tl(loB, src1, 0xffff); + tcg_gen_shri_tl(hiB, src1, 16); + + tcg_gen_andi_tl(loC, src2, 0xffff); + tcg_gen_shri_tl(hiC, src2, 16); + + tcg_gen_sub_tl(loA, loB, loC); + tcg_gen_sub_tl(hiA, hiB, hiC); + + tcg_gen_movcond_tl(TCG_COND_LTU, loA, loA, ctx->msb16, loA, ctx->smax16); + tcg_gen_movcond_tl(TCG_COND_LTU, hiA, hiA, ctx->msb16, hiA, ctx->smax16); + + tcg_gen_deposit_tl(rslt, loA, hiA, 16, 16); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_movi_tl(cpu_Cf, 0); + + gen_sub16_Vf(hiS, hiA, hiB, hiC); + gen_sub16_Vf(loS, loA, loB, loC); + + tcg_gen_or_tl(cpu_Vf, hiS, loS); + tcg_gen_or_tl(cpu_S1f, cpu_S1f, hiS); + tcg_gen_or_tl(cpu_S2f, cpu_S2f, loS); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + tcg_temp_free_i32(loA); + tcg_temp_free_i32(hiA); + tcg_temp_free_i32(loB); + tcg_temp_free_i32(hiB); + tcg_temp_free_i32(loC); + tcg_temp_free_i32(hiC); + tcg_temp_free_i32(hiS); + tcg_temp_free_i32(loS); + + return BS_NONE; +} + diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h index 74beb33..a4699e3 100644 --- a/target-arc/translate-inst.h +++ b/target-arc/translate-inst.h @@ -144,3 +144,7 @@ int arc_gen_JL(DisasCtxt *c, TCGv src1, ARC_COND cond); int arc_gen_LR(DisasCtxt *c, TCGv dest, TCGv src1); int arc_gen_SR(DisasCtxt *c, TCGv src1, TCGv src2); +int arc_gen_ADDS(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_ADDSDW(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_SUBS(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_SUBSDW(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2);