diff mbox

[4/6] target-ppc: add stxsi[bh]x instruction

Message ID 1470591415-3268-5-git-send-email-nikunj@linux.vnet.ibm.com
State New
Headers show

Commit Message

Nikunj A Dadhania Aug. 7, 2016, 5:36 p.m. UTC 
stxsibx - Store VSX Scalar as Integer Byte Indexed
stxsihx - Store VSX Scalar as Integer Halfword Indexed

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/translate.c              | 19 +++++++++++++------
 target-ppc/translate/vsx-impl.inc.c |  2 ++
 target-ppc/translate/vsx-ops.inc.c  |  2 ++
 3 files changed, 17 insertions(+), 6 deletions(-)

Comments

Richard Henderson Aug. 8, 2016, 5:08 a.m. UTC | #1 
On 08/07/2016 11:06 PM, Nikunj A Dadhania wrote:
> +#define GEN_QEMU_STORE_64(stop)                                         \
> +static void gen_qemu_##stop##_i64(DisasContext *ctx,                    \
> +                                  TCGv_i64 val,                         \
> +                                  TCGv addr)                            \
> +{                                                                       \
> +    TCGv tmp = tcg_temp_new();                                          \
> +    tcg_gen_trunc_i64_tl(tmp, val);                                     \
> +    gen_qemu_##stop(ctx, tmp, addr);                                    \
> +    tcg_temp_free(tmp);                                                 \
>  }

Similarly, use tcg_gen_qemu_st_i64.


r~
diff mbox

Patch

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4bdf5ba..cb5bbeb 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2541,14 +2541,21 @@  static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
     tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
 }
 
-static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
-{
-    TCGv tmp = tcg_temp_new();
-    tcg_gen_trunc_i64_tl(tmp, val);
-    gen_qemu_st32(ctx, tmp, addr);
-    tcg_temp_free(tmp);
+#define GEN_QEMU_STORE_64(stop)                                         \
+static void gen_qemu_##stop##_i64(DisasContext *ctx,                    \
+                                  TCGv_i64 val,                         \
+                                  TCGv addr)                            \
+{                                                                       \
+    TCGv tmp = tcg_temp_new();                                          \
+    tcg_gen_trunc_i64_tl(tmp, val);                                     \
+    gen_qemu_##stop(ctx, tmp, addr);                                    \
+    tcg_temp_free(tmp);                                                 \
 }
 
+GEN_QEMU_STORE_64(st8)
+GEN_QEMU_STORE_64(st16)
+GEN_QEMU_STORE_64(st32)
+
 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
 {
     TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index f438a50..fb29e6d 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -118,6 +118,8 @@  static void gen_##name(DisasContext *ctx)                     \
 }
 
 VSX_STORE_SCALAR(stxsdx, st64)
+VSX_STORE_SCALAR(stxsibx, st8_i64)
+VSX_STORE_SCALAR(stxsihx, st16_i64)
 VSX_STORE_SCALAR(stxsiwx, st32_i64)
 VSX_STORE_SCALAR(stxsspx, st32fs)
 
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 4cd742c..414b73b 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -9,6 +9,8 @@  GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
 
 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxsihx, 0x1F, 0xD, 0x1D, 0, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),