From patchwork Tue Aug 2 08:10:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luwei Kang X-Patchwork-Id: 654836 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3s3d6G1pxQz9t3J for ; Tue, 2 Aug 2016 23:56:37 +1000 (AEST) Received: from localhost ([::1]:56759 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUaBO-0000pm-SS for incoming@patchwork.ozlabs.org; Tue, 02 Aug 2016 09:56:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56756) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUUn1-0005iz-RE for qemu-devel@nongnu.org; Tue, 02 Aug 2016 04:11:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bUUmx-0006qB-G7 for qemu-devel@nongnu.org; Tue, 02 Aug 2016 04:11:02 -0400 Received: from mga11.intel.com ([192.55.52.93]:9040) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUUmx-0006q7-AP for qemu-devel@nongnu.org; Tue, 02 Aug 2016 04:10:59 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP; 02 Aug 2016 01:10:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,459,1464678000"; d="scan'208";a="149214483" Received: from vmm-dell.bj.intel.com ([10.238.145.44]) by fmsmga004.fm.intel.com with ESMTP; 02 Aug 2016 01:10:54 -0700 From: Luwei Kang To: qemu-devel@nongnu.org Date: Tue, 2 Aug 2016 16:10:39 +0800 Message-Id: <1470125439-19711-1-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 X-Mailman-Approved-At: Tue, 02 Aug 2016 09:55:04 -0400 Subject: [Qemu-devel] [PATCH] target-i386: add more Intel AVX-512 instructions support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, Luwei Kang , ehabkost@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add more AVX512 feature bits, include AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, AVX512VBMI. Its spec can be found at: https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf Signed-off-by: Luwei Kang --- target-i386/cpu.c | 14 +++++++++----- target-i386/cpu.h | 5 +++++ 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 6a1afab..ec674dc 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -298,14 +298,18 @@ static const char *svm_feature_name[] = { }; static const char *cpuid_7_0_ebx_feature_name[] = { - "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep", - "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL, - "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt", - "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL, + "fsgsbase", "tsc_adjust", NULL, "bmi1", + "hle", "avx2", NULL, "smep", + "bmi2", "erms", "invpcid", "rtm", + NULL, NULL, "mpx", NULL, + "avx512f", "avx512dq", "rdseed", "adx", + "smap", "avx512ifma", "pcommit", "clflushopt", + "clwb", NULL, "avx512pf", "avx512er", + "avx512cd", NULL, "avx512bw", "avx512vl", }; static const char *cpuid_7_0_ecx_feature_name[] = { - NULL, NULL, "umip", "pku", + NULL, "avx512vbmi", "umip", "pku", "ospke", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 65615c0..cf14bcb 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -606,16 +606,21 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_RTM (1U << 11) #define CPUID_7_0_EBX_MPX (1U << 14) #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ +#define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ #define CPUID_7_0_EBX_RDSEED (1U << 18) #define CPUID_7_0_EBX_ADX (1U << 19) #define CPUID_7_0_EBX_SMAP (1U << 20) +#define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ +#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ +#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ +#define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ #define CPUID_7_0_ECX_UMIP (1U << 2) #define CPUID_7_0_ECX_PKU (1U << 3) #define CPUID_7_0_ECX_OSPKE (1U << 4)