From patchwork Tue Jul 26 03:28:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Xu X-Patchwork-Id: 652561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rz3XM1VL1z9ssM for ; Tue, 26 Jul 2016 13:29:53 +1000 (AEST) Received: from localhost ([::1]:37198 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bRt40-0000F7-St for incoming@patchwork.ozlabs.org; Mon, 25 Jul 2016 23:29:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bRt3M-0008IE-6t for qemu-devel@nongnu.org; Mon, 25 Jul 2016 23:29:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bRt3H-00060Y-5b for qemu-devel@nongnu.org; Mon, 25 Jul 2016 23:29:07 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55690) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bRt3G-00060U-TN for qemu-devel@nongnu.org; Mon, 25 Jul 2016 23:29:03 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C98E313A46; Tue, 26 Jul 2016 03:29:01 +0000 (UTC) Received: from pxdev.nay.redhat.com (dhcp-14-175.nay.redhat.com [10.66.14.175]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u6Q3SxjJ022585; Mon, 25 Jul 2016 23:29:00 -0400 From: Peter Xu To: qemu-devel@nongnu.org Date: Tue, 26 Jul 2016 11:28:58 +0800 Message-Id: <1469503738-28269-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 26 Jul 2016 03:29:01 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2] x86: ioapic: conditionally upgrade IOAPIC version X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, pbonzini@redhat.com, peterx@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" IOMMU IR and IOAPIC legacy devices (e.g., e1000) cannot work well together with some old Linux kernels (upstream before v4.0, or any released RHEL kernels). This patch fixes it. The problem is that: some old linux kernels (with IR enabled) only support IOAPIC chips with version 0x20. New kernels after commit d32932d ("x86/irq: Convert IOAPIC to use hierarchical irqdomain interfaces") fixed this problem. To make sure we can work with even old kernels, let's upgrade our IOAPIC to version 0x20. To make sure we have minimum impact on old systems, IOAPIC version is only boosted to 0x20 when vIOMMU IR is enabled. Besides that, the old version 0x11 is used. Signed-off-by: Peter Xu --- hw/intc/ioapic.c | 25 ++++++++++++++++++++++++- include/hw/i386/ioapic_internal.h | 3 +-- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 2d3282a..cd3f283 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -244,6 +244,23 @@ void ioapic_dump_state(Monitor *mon, const QDict *qdict) } } +static uint32_t ioapic_get_version(void) +{ + X86IOMMUState *iommu = x86_iommu_get_default(); + + /* + * If we enabled vIOMMU IR, we provide a upgraded version of + * IOAPIC 0x20, which support explicit EOI request from guest. + * This fixes a bug that IR not working on some old upstream + * kernels (before v4.0, commit d32932d) or most RHEL ones. + */ + if (iommu && iommu->intr_supported) { + return 0x20; + } + + return 0x11; +} + static uint64_t ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size) { @@ -265,7 +282,7 @@ ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size) val = s->id << IOAPIC_ID_SHIFT; break; case IOAPIC_REG_VER: - val = IOAPIC_VERSION | + val = ioapic_get_version() | ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); break; default: @@ -354,6 +371,12 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, } } break; + case IOAPIC_EOI: + if (size != 4 || ioapic_get_version() != 0x20) { + break; + } + ioapic_eoi_broadcast(val); + break; } ioapic_update_kvm_routes(s); diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index d89ea1b..6f266c3 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -29,8 +29,6 @@ #define MAX_IOAPICS 1 -#define IOAPIC_VERSION 0x11 - #define IOAPIC_LVT_DEST_SHIFT 56 #define IOAPIC_LVT_DEST_IDX_SHIFT 48 #define IOAPIC_LVT_MASKED_SHIFT 16 @@ -71,6 +69,7 @@ #define IOAPIC_IOREGSEL 0x00 #define IOAPIC_IOWIN 0x10 +#define IOAPIC_EOI 0x40 #define IOAPIC_REG_ID 0x00 #define IOAPIC_REG_VER 0x01