From patchwork Mon Jul 18 09:27:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 649433 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rtJ9p6KCHz9s5J for ; Mon, 18 Jul 2016 19:42:22 +1000 (AEST) Received: from localhost ([::1]:45450 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bP548-0004fC-Rj for incoming@patchwork.ozlabs.org; Mon, 18 Jul 2016 05:42:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36324) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bP4qi-0004Uo-SD for qemu-devel@nongnu.org; Mon, 18 Jul 2016 05:28:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bP4qd-0006ac-1w for qemu-devel@nongnu.org; Mon, 18 Jul 2016 05:28:27 -0400 Received: from mx1.redhat.com ([209.132.183.28]:58867) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bP4qc-0006aY-Ph for qemu-devel@nongnu.org; Mon, 18 Jul 2016 05:28:22 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6646F7F352; Mon, 18 Jul 2016 09:28:22 +0000 (UTC) Received: from donizetti.redhat.com (ovpn-112-56.ams2.redhat.com [10.36.112.56]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u6I9RuJ8025611; Mon, 18 Jul 2016 05:28:20 -0400 From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Mon, 18 Jul 2016 11:27:45 +0200 Message-Id: <1468834075-25669-14-git-send-email-pbonzini@redhat.com> In-Reply-To: <1468834075-25669-1-git-send-email-pbonzini@redhat.com> References: <1468834075-25669-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Mon, 18 Jul 2016 09:28:22 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 13/23] target-i386: Remove redundant HF_SOFTMMU_MASK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sergey Fedorov , Sergey Fedorov Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sergey Fedorov 'HF_SOFTMMU_MASK' is only set when 'CONFIG_SOFTMMU' is defined. So there's no need in this flag: test 'CONFIG_SOFTMMU' instead. Suggested-by: Paolo Bonzini Signed-off-by: Sergey Fedorov Signed-off-by: Sergey Fedorov Reviewed-by: Alex Bennée Message-Id: <20160715175852.30749-6-sergey.fedorov@linaro.org> Signed-off-by: Paolo Bonzini --- target-i386/cpu.c | 3 --- target-i386/cpu.h | 3 --- target-i386/translate.c | 12 ++++-------- 3 files changed, 4 insertions(+), 14 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index fc209ee..6e49e4c 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2725,9 +2725,6 @@ static void x86_cpu_reset(CPUState *s) /* init to reset state */ -#ifdef CONFIG_SOFTMMU - env->hflags |= HF_SOFTMMU_MASK; -#endif env->hflags2 |= HF2_GIF_MASK; cpu_x86_update_cr0(env, 0x60000010); diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 776efe6..5b14a72 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -130,8 +130,6 @@ positions to ease oring with eflags. */ /* current cpl */ #define HF_CPL_SHIFT 0 -/* true if soft mmu is being used */ -#define HF_SOFTMMU_SHIFT 2 /* true if hardware interrupts must be disabled for next instruction */ #define HF_INHIBIT_IRQ_SHIFT 3 /* 16 or 32 segments */ @@ -161,7 +159,6 @@ #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ #define HF_CPL_MASK (3 << HF_CPL_SHIFT) -#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) #define HF_CS32_MASK (1 << HF_CS32_SHIFT) #define HF_SS32_MASK (1 << HF_SS32_SHIFT) diff --git a/target-i386/translate.c b/target-i386/translate.c index 7dea18b..e81fce7 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -8224,9 +8224,9 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) dc->popl_esp_hack = 0; /* select memory access functions */ dc->mem_index = 0; - if (flags & HF_SOFTMMU_MASK) { - dc->mem_index = cpu_mmu_index(env, false); - } +#ifdef CONFIG_SOFTMMU + dc->mem_index = cpu_mmu_index(env, false); +#endif dc->cpuid_features = env->features[FEAT_1_EDX]; dc->cpuid_ext_features = env->features[FEAT_1_ECX]; dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX]; @@ -8239,11 +8239,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) #endif dc->flags = flags; dc->jmp_opt = !(dc->tf || cs->singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK) -#ifndef CONFIG_SOFTMMU - || (flags & HF_SOFTMMU_MASK) -#endif - ); + (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths in !repz_opt and repz_opt modes. The first one was used