From patchwork Tue Jul 12 11:14:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 647347 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rpfw62L1Qz9s9N for ; Tue, 12 Jul 2016 21:32:54 +1000 (AEST) Received: from localhost ([::1]:39159 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMvvn-0000eD-Fm for incoming@patchwork.ozlabs.org; Tue, 12 Jul 2016 07:32:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47950) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMvfO-0005xZ-OG for qemu-devel@nongnu.org; Tue, 12 Jul 2016 07:15:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bMvfI-00022w-Gk for qemu-devel@nongnu.org; Tue, 12 Jul 2016 07:15:53 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:36573) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMvfI-00022s-Aa for qemu-devel@nongnu.org; Tue, 12 Jul 2016 07:15:48 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id C6CBA8C61B486 for ; Tue, 12 Jul 2016 12:15:43 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 12 Jul 2016 12:15:46 +0100 From: Leon Alrae To: Date: Tue, 12 Jul 2016 12:14:55 +0100 Message-ID: <1468322097-2315-10-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1468322097-2315-1-git-send-email-leon.alrae@imgtec.com> References: <1468322097-2315-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 09/11] target-mips: change ASID type to hold more than 8 bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Burton Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Paul Burton ASID currently has uint8_t type which is too small since some processors support more than 8 bits ASID. Therefore change its type to uint16_t. Signed-off-by: Paul Burton Signed-off-by: James Hogan Signed-off-by: Leon Alrae --- target-mips/cpu.h | 2 +- target-mips/helper.c | 4 ++-- target-mips/machine.c | 10 +++++----- target-mips/op_helper.c | 8 ++++---- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 6325e15..3e233ad 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -19,7 +19,7 @@ typedef struct r4k_tlb_t r4k_tlb_t; struct r4k_tlb_t { target_ulong VPN; uint32_t PageMask; - uint8_t ASID; + uint16_t ASID; unsigned int G:1; unsigned int C0:3; unsigned int C1:3; diff --git a/target-mips/helper.c b/target-mips/helper.c index 1e194e9..9fbca26 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -67,7 +67,7 @@ int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type) { - uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; int i; for (i = 0; i < env->tlb->tlb_in_use; i++) { @@ -898,7 +898,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) r4k_tlb_t *tlb; target_ulong addr; target_ulong end; - uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; target_ulong mask; tlb = &env->tlb->mmu.r4k.tlb[idx]; diff --git a/target-mips/machine.c b/target-mips/machine.c index 7314cfe..a27f2f1 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -132,7 +132,7 @@ static int get_tlb(QEMUFile *f, void *pv, size_t size) qemu_get_betls(f, &v->VPN); qemu_get_be32s(f, &v->PageMask); - qemu_get_8s(f, &v->ASID); + qemu_get_be16s(f, &v->ASID); qemu_get_be16s(f, &flags); v->G = (flags >> 10) & 1; v->C0 = (flags >> 7) & 3; @@ -156,7 +156,7 @@ static void put_tlb(QEMUFile *f, void *pv, size_t size) { r4k_tlb_t *v = pv; - uint8_t asid = v->ASID; + uint16_t asid = v->ASID; uint16_t flags = ((v->EHINV << 15) | (v->RI1 << 14) | (v->RI0 << 13) | @@ -172,7 +172,7 @@ static void put_tlb(QEMUFile *f, void *pv, size_t size) qemu_put_betls(f, &v->VPN); qemu_put_be32s(f, &v->PageMask); - qemu_put_8s(f, &asid); + qemu_put_be16s(f, &asid); qemu_put_be16s(f, &flags); qemu_put_be64s(f, &v->PFN[0]); qemu_put_be64s(f, &v->PFN[1]); @@ -192,8 +192,8 @@ const VMStateInfo vmstate_info_tlb = { const VMStateDescription vmstate_tlb = { .name = "cpu/tlb", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext), VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext), diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 1562f22..31c85f9 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2013,7 +2013,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env) { int idx; r4k_tlb_t *tlb; - uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; for (idx = 0; idx < env->tlb->nb_tlb; idx++) { tlb = &env->tlb->mmu.r4k.tlb[idx]; @@ -2039,7 +2039,7 @@ void r4k_helper_tlbwi(CPUMIPSState *env) r4k_tlb_t *tlb; int idx; target_ulong VPN; - uint8_t ASID; + uint16_t ASID; bool G, V0, D0, V1, D1; idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; @@ -2081,7 +2081,7 @@ void r4k_helper_tlbp(CPUMIPSState *env) target_ulong mask; target_ulong tag; target_ulong VPN; - uint8_t ASID; + uint16_t ASID; int i; ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; @@ -2136,7 +2136,7 @@ static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) void r4k_helper_tlbr(CPUMIPSState *env) { r4k_tlb_t *tlb; - uint8_t ASID; + uint16_t ASID; int idx; ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;