From patchwork Mon Jul 4 19:16:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dr. David Alan Gilbert" X-Patchwork-Id: 644382 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rjxlD317kz9sdb for ; Tue, 5 Jul 2016 05:23:52 +1000 (AEST) Received: from localhost ([::1]:50062 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bK9TC-0003eh-Bt for incoming@patchwork.ozlabs.org; Mon, 04 Jul 2016 15:23:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39460) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bK9Lx-0008Q5-4e for qemu-devel@nongnu.org; Mon, 04 Jul 2016 15:16:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bK9Lv-0003Rr-31 for qemu-devel@nongnu.org; Mon, 04 Jul 2016 15:16:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:32985) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bK9Lu-0003Ri-Qk for qemu-devel@nongnu.org; Mon, 04 Jul 2016 15:16:19 -0400 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 697F77F342 for ; Mon, 4 Jul 2016 19:16:18 +0000 (UTC) Received: from dgilbert-t530.redhat.com (ovpn-116-105.ams2.redhat.com [10.36.116.105]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u64JG9Ce015622; Mon, 4 Jul 2016 15:16:17 -0400 From: "Dr. David Alan Gilbert (git)" To: qemu-devel@nongnu.org, pbonzini@redhat.com, ehabkost@redhat.com, marcel@redhat.com, mst@redhat.com, kraxel@redhat.com Date: Mon, 4 Jul 2016 20:16:07 +0100 Message-Id: <1467659769-15900-5-git-send-email-dgilbert@redhat.com> In-Reply-To: <1467659769-15900-1-git-send-email-dgilbert@redhat.com> References: <1467659769-15900-1-git-send-email-dgilbert@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Mon, 04 Jul 2016 19:16:18 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 4/6] x86: Set physical address bits based on host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Dr. David Alan Gilbert" A special case based on the previous phys-bits property; if it's the magic value 0 then use the hosts capabilities. This becomes the default on new machine types. Signed-off-by: Dr. David Alan Gilbert --- include/hw/i386/pc.h | 5 +++++ target-i386/cpu.c | 36 +++++++++++++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index d85e924..bf31609 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -379,6 +379,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = TYPE_X86_CPU,\ .property = "fill-mtrr-mask",\ .value = "off",\ + },\ + {\ + .driver = TYPE_X86_CPU,\ + .property = "phys-bits",\ + .value = "40",\ }, #define PC_COMPAT_2_5 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 5737aba..d45d2a6 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2957,6 +2957,40 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) & CPUID_EXT2_AMD_ALIASES); } + /* For 64bit systems think about the number of physical bits to present. + * ideally this should be the same as the host; anything other than matching + * the host can cause incorrect guest behaviour. + * QEMU used to pick the magic value of 40 bits that corresponds to + * consumer AMD devices but nothing esle. + */ + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + uint32_t eax; + /* Read the hosts physical address size, and compare it to what we + * were asked for; note old machine types default to 40 bits + */ + uint32_t host_phys_bits = 0; + host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); + if (eax >= 0x80000008) { + host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); + /* Note: According to AMD doc 25481 rev 2.34 they have a field + * at 23:16 that can specify a maximum physical address bits for + * the guest that can override this value; but I've not seen + * anything with that set. + */ + host_phys_bits = eax & 0xff; + } else { + /* It's an odd 64 bit machine that doesn't have the leaf for + * physical address bits; fall back to 36 that's most older Intel. + */ + host_phys_bits = 36; + } + + if (cpu->phys_bits == 0) { + /* The user asked for us to use the host physical bits */ + cpu->phys_bits = host_phys_bits; + + } + } cpu_exec_init(cs, &error_abort); @@ -3259,7 +3293,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), - DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 40), + DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0), DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0), DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),