From patchwork Mon Jun 27 19:01:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emilio Cota X-Patchwork-Id: 641215 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rdf6x64j5z9syB for ; Tue, 28 Jun 2016 05:26:01 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=braap.org header.i=@braap.org header.b=XjGO9LOI; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b=PCZeJL37; dkim-atps=neutral Received: from localhost ([::1]:60630 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHcAR-0000Z7-Gt for incoming@patchwork.ozlabs.org; Mon, 27 Jun 2016 15:25:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHboA-0006fT-He for qemu-devel@nongnu.org; Mon, 27 Jun 2016 15:03:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHbo6-0008HB-SK for qemu-devel@nongnu.org; Mon, 27 Jun 2016 15:02:57 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:59786) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHbo5-0008CS-H1 for qemu-devel@nongnu.org; Mon, 27 Jun 2016 15:02:54 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id BF9CA208C0; Mon, 27 Jun 2016 15:02:33 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Mon, 27 Jun 2016 15:02:33 -0400 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-sasl-enc:x-sasl-enc; s=mesmtp; bh=6tFsyvcHW9C8yQLR5zQeoDbnWus =; b=XjGO9LOIIkfu8GgnKRZXe5bR7JIU8T8s3Wgpc2c7ik+qSmS0TBlrCezEP42 MIgMvqFtPxnV9wYF9f/GmDvtkNQiaYhMfNsnqf7ngh4Swi6dVkIJWfVWiXrAakcu Odj6WVDRPxyCirJA2JPTrEVoEVj23bSku9DMLUXEXCP50aVU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-sasl-enc:x-sasl-enc; s=smtpout; bh=6tFs yvcHW9C8yQLR5zQeoDbnWus=; b=PCZeJL37x9LuYyv7SCscRLQcfk6ThY8yKA7i fFylp3L+RLwIk4V87uGfoVNoioGuz6CyVRy9f93O+KrQV4JdD0u8vph6jYAl/fBq x1PbSE8Z7csWw/5MgAEw/n+3g4ILNtbzd/CebsBWbZ+Azc2HICn/kRrHgABRT/9w 0tvIXWs= X-Sasl-enc: YmnaEbYGxq9aWDhe0Cg3PwQkJgmZ4fExLiGNElfdhXO6 1467054153 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 6A963F2A08; Mon, 27 Jun 2016 15:02:33 -0400 (EDT) From: "Emilio G. Cota" To: QEMU Developers , MTTCG Devel Date: Mon, 27 Jun 2016 15:01:57 -0400 Message-Id: <1467054136-10430-12-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1467054136-10430-1-git-send-email-cota@braap.org> References: <1467054136-10430-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC 11/30] target-i386: add atomic helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alvise Rigo , Sergey Fedorov , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This patch only adds the helpers. Functions to invoke the helpers from translated code are generated in subsequent patches. Signed-off-by: Emilio G. Cota --- target-i386/helper.h | 34 ++++++++++++++++++++++++++++++++++ target-i386/mem_helper.c | 38 ++++++++++++++++++++++++++++++++++++++ target-i386/translate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 117 insertions(+) diff --git a/target-i386/helper.h b/target-i386/helper.h index 2bb0d1f..df68204 100644 --- a/target-i386/helper.h +++ b/target-i386/helper.h @@ -84,6 +84,40 @@ DEF_HELPER_4(cmpxchgq, tl, env, tl, tl, tl) DEF_HELPER_2(cmpxchg16b, void, env, tl) DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) #endif + +/* + * Use glue(foo, glue(bar, baz)) instead of glue(glue(foo, bar), baz), otherwise + * some gcc's (e.g. v4.6.3) can get confused with the surrounding DEF_HELPER. + */ +#ifndef TARGET_X86_64 +#define DEF_ATOMIC_ALL(NAME) \ + DEF_HELPER_3(glue(atomic_, glue(NAME, b)), tl, env, tl, tl) \ + DEF_HELPER_3(glue(atomic_, glue(NAME, w)), tl, env, tl, tl) \ + DEF_HELPER_3(glue(atomic_, glue(NAME, l)), tl, env, tl, tl) +#else /* 64-bit */ +#define DEF_ATOMIC_ALL(NAME) \ + DEF_HELPER_3(glue(atomic_, glue(NAME, b)), tl, env, tl, tl) \ + DEF_HELPER_3(glue(atomic_, glue(NAME, w)), tl, env, tl, tl) \ + DEF_HELPER_3(glue(atomic_, glue(NAME, l)), tl, env, tl, tl) \ + DEF_HELPER_3(glue(atomic_, glue(NAME, q)), tl, env, tl, tl) +#endif + +DEF_ATOMIC_ALL(fetch_add) +DEF_ATOMIC_ALL(fetch_and) +DEF_ATOMIC_ALL(fetch_or) +DEF_ATOMIC_ALL(fetch_sub) +DEF_ATOMIC_ALL(fetch_xor) + +DEF_ATOMIC_ALL(add_fetch) +DEF_ATOMIC_ALL(and_fetch) +DEF_ATOMIC_ALL(or_fetch) +DEF_ATOMIC_ALL(sub_fetch) +DEF_ATOMIC_ALL(xor_fetch) + +DEF_ATOMIC_ALL(xchg) + +#undef DEF_ATOMIC_ALL + DEF_HELPER_1(single_step, void, env) DEF_HELPER_1(cpuid, void, env) DEF_HELPER_1(rdtsc, void, env) diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c index b002aba..13f4f3b 100644 --- a/target-i386/mem_helper.c +++ b/target-i386/mem_helper.c @@ -170,6 +170,44 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) } #endif +#define GEN_ATOMIC_HELPER(NAME) \ +target_ulong \ +glue(helper_atomic_, \ + NAME)(CPUArchState *env, target_ulong addr, target_ulong val) \ +{ \ + return glue(glue(cpu_atomic_, NAME), _data_ra)(env, addr, val, GETPC()); \ +} + +#ifndef TARGET_X86_64 +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(glue(NAME, b)) \ + GEN_ATOMIC_HELPER(glue(NAME, w)) \ + GEN_ATOMIC_HELPER(glue(NAME, l)) +#else /* 64-bit */ +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(glue(NAME, b)) \ + GEN_ATOMIC_HELPER(glue(NAME, w)) \ + GEN_ATOMIC_HELPER(glue(NAME, l)) \ + GEN_ATOMIC_HELPER(glue(NAME, q)) +#endif /* TARGET_X86_64 */ + +GEN_ATOMIC_HELPER_ALL(fetch_add) +GEN_ATOMIC_HELPER_ALL(fetch_and) +GEN_ATOMIC_HELPER_ALL(fetch_or) +GEN_ATOMIC_HELPER_ALL(fetch_sub) +GEN_ATOMIC_HELPER_ALL(fetch_xor) + +GEN_ATOMIC_HELPER_ALL(add_fetch) +GEN_ATOMIC_HELPER_ALL(and_fetch) +GEN_ATOMIC_HELPER_ALL(or_fetch) +GEN_ATOMIC_HELPER_ALL(sub_fetch) +GEN_ATOMIC_HELPER_ALL(xor_fetch) + +GEN_ATOMIC_HELPER_ALL(xchg) + +#undef GEN_ATOMIC_HELPER +#undef GEN_ATOMIC_HELPER_ALL + void helper_boundw(CPUX86State *env, target_ulong a0, int v) { int low, high; diff --git a/target-i386/translate.c b/target-i386/translate.c index 9abd82f..eead9d7 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -1271,6 +1271,51 @@ static void gen_cmpxchg(TCGv ret, TCGv addr, TCGv old, TCGv new, TCGMemOp ot) } } +#ifndef TARGET_X86_64 +#define GEN_ATOMIC_HELPER(NAME) \ +static void \ +glue(gen_atomic_, NAME)(TCGv ret, TCGv addr, TCGv reg, TCGMemOp ot) \ +{ \ + switch (ot & 3) { \ + case 0: \ + glue(glue(gen_helper_atomic_, NAME), b)(ret, cpu_env, addr, reg); \ + break; \ + case 1: \ + glue(glue(gen_helper_atomic_, NAME), w)(ret, cpu_env, addr, reg); \ + break; \ + case 2: \ + glue(glue(gen_helper_atomic_, NAME), l)(ret, cpu_env, addr, reg); \ + break; \ + default: \ + tcg_abort(); \ + } \ +} +#else /* 64-bit */ +#define GEN_ATOMIC_HELPER(NAME) \ +static void \ +glue(gen_atomic_, NAME)(TCGv ret, TCGv addr, TCGv reg, TCGMemOp ot) \ +{ \ + switch (ot & 3) { \ + case 0: \ + glue(glue(gen_helper_atomic_, NAME), b)(ret, cpu_env, addr, reg); \ + break; \ + case 1: \ + glue(glue(gen_helper_atomic_, NAME), w)(ret, cpu_env, addr, reg); \ + break; \ + case 2: \ + glue(glue(gen_helper_atomic_, NAME), l)(ret, cpu_env, addr, reg); \ + break; \ + case 3: \ + glue(glue(gen_helper_atomic_, NAME), q)(ret, cpu_env, addr, reg); \ + break; \ + default: \ + tcg_abort(); \ + } \ +} +#endif /* TARGET_X86_64 */ + +#undef GEN_ATOMIC_HELPER + /* if d == OR_TMP0, it means memory operand (address in A0) */ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) {