From patchwork Mon Jun 27 15:19:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 641106 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rdXnx1vSLz9sBG for ; Tue, 28 Jun 2016 01:25:57 +1000 (AEST) Received: from localhost ([::1]:59333 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYQ7-0007at-0V for incoming@patchwork.ozlabs.org; Mon, 27 Jun 2016 11:25:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47460) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYJw-0001oE-TM for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHYJr-0001Eb-CN for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:31 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:21685) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYJr-0001EU-2F for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:27 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id A13D7881F04A; Mon, 27 Jun 2016 16:19:21 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 27 Jun 2016 16:19:24 +0100 From: Leon Alrae To: Date: Mon, 27 Jun 2016 16:19:09 +0100 Message-ID: <1467040752-18666-2-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1467040752-18666-1-git-send-email-leon.alrae@imgtec.com> References: <1467040752-18666-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH 1/4] target-mips: add ASID mask field and replace magic values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Hogan , Paul Burton , aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Paul Burton Signed-off-by: Paul Burton Signed-off-by: James Hogan Signed-off-by: Leon Alrae --- target-mips/cpu.h | 2 ++ target-mips/helper.c | 10 +++++----- target-mips/op_helper.c | 27 +++++++++++++++------------ target-mips/translate.c | 1 + 4 files changed, 23 insertions(+), 17 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index c2e3586..72053b3 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -343,6 +343,7 @@ struct CPUMIPSState { int32_t CP0_Count; target_ulong CP0_EntryHi; #define CP0EnHi_EHINV 10 + target_ulong CP0_EntryHi_ASID_mask; int32_t CP0_Compare; int32_t CP0_Status; #define CP0St_CU3 31 @@ -503,6 +504,7 @@ struct CPUMIPSState { int CP0_LLAddr_shift; target_ulong CP0_WatchLo[8]; int32_t CP0_WatchHi[8]; +#define CP0WH_ASID 16 target_ulong CP0_XContext; int32_t CP0_Framemask; int32_t CP0_Debug; diff --git a/target-mips/helper.c b/target-mips/helper.c index 1402ff0..1e194e9 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -67,7 +67,7 @@ int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type) { - uint8_t ASID = env->CP0_EntryHi & 0xFF; + uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; int i; for (i = 0; i < env->tlb->tlb_in_use; i++) { @@ -249,7 +249,7 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) cu = (v >> CP0St_CU0) & 0xf; mx = (v >> CP0St_MX) & 0x1; ksu = (v >> CP0St_KSU) & 0x3; - asid = env->CP0_EntryHi & 0xff; + asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; tcstatus = cu << CP0TCSt_TCU0; tcstatus |= mx << CP0TCSt_TMX; @@ -395,8 +395,8 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, env->CP0_BadVAddr = address; env->CP0_Context = (env->CP0_Context & ~0x007fffff) | ((address >> 9) & 0x007ffff0); - env->CP0_EntryHi = - (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); + env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | + (address & (TARGET_PAGE_MASK << 1)); #if defined(TARGET_MIPS64) env->CP0_EntryHi &= env->SEGMask; env->CP0_XContext = @@ -898,7 +898,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) r4k_tlb_t *tlb; target_ulong addr; target_ulong end; - uint8_t ASID = env->CP0_EntryHi & 0xFF; + uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; target_ulong mask; tlb = &env->tlb->mmu.r4k.tlb[idx]; diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 69daade..1562f22 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -679,7 +679,7 @@ static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, tcu = (v >> CP0TCSt_TCU0) & 0xf; tmx = (v >> CP0TCSt_TMX) & 0x1; - tasid = v & 0xff; + tasid = v & cpu->CP0_EntryHi_ASID_mask; tksu = (v >> CP0TCSt_TKSU) & 0x3; status = tcu << CP0St_CU0; @@ -690,7 +690,7 @@ static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, cpu->CP0_Status |= status; /* Sync the TASID with EntryHi. */ - cpu->CP0_EntryHi &= ~0xff; + cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask; cpu->CP0_EntryHi |= tasid; compute_hflags(cpu); @@ -702,7 +702,7 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) int32_t *tcst; uint32_t asid, v = cpu->CP0_EntryHi; - asid = v & 0xff; + asid = v & cpu->CP0_EntryHi_ASID_mask; if (tc == cpu->current_tc) { tcst = &cpu->active_tc.CP0_TCStatus; @@ -710,7 +710,7 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) tcst = &cpu->tcs[tc].CP0_TCStatus; } - *tcst &= ~0xff; + *tcst &= ~cpu->CP0_EntryHi_ASID_mask; *tcst |= asid; } @@ -1403,7 +1403,7 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; - mask = (TARGET_PAGE_MASK << 1) | 0xFF; + mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask; if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) { mask |= 1 << CP0EnHi_EHINV; } @@ -1429,8 +1429,10 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) sync_c0_entryhi(env, env->current_tc); } /* If the ASID changes, flush qemu's TLB. */ - if ((old & 0xFF) != (val & 0xFF)) + if ((old & env->CP0_EntryHi_ASID_mask) != + (val & env->CP0_EntryHi_ASID_mask)) { cpu_mips_tlb_flush(env, 1); + } } void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) @@ -1631,7 +1633,8 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { - env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8); + int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); + env->CP0_WatchHi[sel] = arg1 & mask; env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); } @@ -1989,7 +1992,7 @@ static void r4k_fill_tlb(CPUMIPSState *env, int idx) #if defined(TARGET_MIPS64) tlb->VPN &= env->SEGMask; #endif - tlb->ASID = env->CP0_EntryHi & 0xFF; + tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; tlb->PageMask = env->CP0_PageMask; tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; @@ -2010,7 +2013,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env) { int idx; r4k_tlb_t *tlb; - uint8_t ASID = env->CP0_EntryHi & 0xFF; + uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; for (idx = 0; idx < env->tlb->nb_tlb; idx++) { tlb = &env->tlb->mmu.r4k.tlb[idx]; @@ -2045,7 +2048,7 @@ void r4k_helper_tlbwi(CPUMIPSState *env) #if defined(TARGET_MIPS64) VPN &= env->SEGMask; #endif - ASID = env->CP0_EntryHi & 0xff; + ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; V0 = (env->CP0_EntryLo0 & 2) != 0; D0 = (env->CP0_EntryLo0 & 4) != 0; @@ -2081,7 +2084,7 @@ void r4k_helper_tlbp(CPUMIPSState *env) uint8_t ASID; int i; - ASID = env->CP0_EntryHi & 0xFF; + ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; for (i = 0; i < env->tlb->nb_tlb; i++) { tlb = &env->tlb->mmu.r4k.tlb[i]; /* 1k pages are not supported. */ @@ -2136,7 +2139,7 @@ void r4k_helper_tlbr(CPUMIPSState *env) uint8_t ASID; int idx; - ASID = env->CP0_EntryHi & 0xFF; + ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; tlb = &env->tlb->mmu.r4k.tlb[idx]; diff --git a/target-mips/translate.c b/target-mips/translate.c index c302fa3..01510b3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20302,6 +20302,7 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { env->CP0_CMGCRBase = 0x1fbf8000 >> 4; } + env->CP0_EntryHi_ASID_mask = 0xff; env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); /* vectored interrupts not implemented, timer on int 7, no performance counters. */