From patchwork Sun Jun 12 19:01:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Rolnik X-Patchwork-Id: 634210 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rSQRQ1HMgz9sDG for ; Mon, 13 Jun 2016 05:08:18 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=lTBKIW/x; dkim-atps=neutral Received: from localhost ([::1]:52396 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCAk4-0006Dn-5G for incoming@patchwork.ozlabs.org; Sun, 12 Jun 2016 15:08:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52977) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCAeT-000145-0s for qemu-devel@nongnu.org; Sun, 12 Jun 2016 15:02:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCAeP-0000o1-TC for qemu-devel@nongnu.org; Sun, 12 Jun 2016 15:02:29 -0400 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:36370) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCAeO-0000nr-UW for qemu-devel@nongnu.org; Sun, 12 Jun 2016 15:02:25 -0400 Received: by mail-wm0-x243.google.com with SMTP id m124so10083116wme.3 for ; Sun, 12 Jun 2016 12:02:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2MhLEHo96Aa0SU1J7sRIAniE0Lm438DSK/iyHwD+t8I=; b=lTBKIW/xRoXnf4fAIeR8V/3KWesh2/d2KUnUmI/Kt2iFgX5OauFPcFNNBiCH9zVCfx 8mSG3ueqb5WAanwcfLXFqZKAwBL8jHTomj9CJPYU+52bo43WX27wu14QFrm+5g4ohdGv C9ASXgOu2BRx1d0+qwpP6vVsB4/6ws9otMVmJBTOk2w5go59kfZ6vJ8Tj564kQtOAxRp d/Tsg2xIsdBhlk3X/Md/qq/4aSF0Fg2xEmJVSTiVvDphvrgvh0IJnvUkN+taL2EnvqZj 5EvFnpTJLpFPUyHGsFcLuQvg3WNCpm4IXaJzi0r5yhGlRZEhZjgc7HUD0etxED3Jp//f WmbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2MhLEHo96Aa0SU1J7sRIAniE0Lm438DSK/iyHwD+t8I=; b=RtHshXoUD/NWVsTd0EWns2ksboio4Z71tLpoYoBDrp0bJAvYUoDaeyFMP9WYeBNzXg 8d0f9RsJrE8lhNqyOh4S9i0EuoKUhr25IAYLPqNuTo2fnhLv8dfAVNY0E10qW44R8Vf6 BtkEdrdx7Mex3oqhrLtdkGUyvajwspscj4BRfTQdzJkEHwvIuOHEzq/AvsDpZJ6F7do9 EGnTQ5m4YYB/K831MvFmo5Wpd+pp7KBsWMuhINWvt3YJXd8c14ASBEUbTADt7V3oZEjP gDzWquLLdEHAyTOG/nGz5MuqPo8ggy2osA8S15liIsq52wwrqOu3g06/U3ugWib2EhFL Fn+A== X-Gm-Message-State: ALyK8tLVz6a9N7gCXYUEaGu8fsUGShe7eNy9uIlxvvpihKidur/h19xn83+F3jyX42p72w== X-Received: by 10.28.45.142 with SMTP id t136mr2608384wmt.40.1465758143947; Sun, 12 Jun 2016 12:02:23 -0700 (PDT) Received: from a0999b0126e1.ant.amazon.com ([5.102.195.79]) by smtp.gmail.com with ESMTPSA id z6sm23491129wjv.41.2016.06.12.12.02.22 (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 12 Jun 2016 12:02:22 -0700 (PDT) From: Michael Rolnik To: qemu-devel@nongnu.org Date: Sun, 12 Jun 2016 22:01:44 +0300 Message-Id: <1465758111-60131-5-git-send-email-mrolnik@gmail.com> X-Mailer: git-send-email 2.4.9 (Apple Git-60) In-Reply-To: <1465758111-60131-1-git-send-email-mrolnik@gmail.com> References: <1465758111-60131-1-git-send-email-mrolnik@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v6 04/11] target-avr: adding instructions encodings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Michael Rolnik , rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Michael Rolnik Signed-off-by: Michael Rolnik --- target-avr/translate-inst.h | 762 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 762 insertions(+) create mode 100644 target-avr/translate-inst.h diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h new file mode 100644 index 0000000..0c082d3 --- /dev/null +++ b/target-avr/translate-inst.h @@ -0,0 +1,762 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2016 Michael Rolnik + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + + +#ifndef AVR_TRANSLATE_INST_H_ +#define AVR_TRANSLATE_INST_H_ + +typedef struct DisasContext DisasContext; + +int avr_translate_NOP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_MOVW(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t MOVW_Rr(uint32_t opcode) +{ + return extract32(opcode, 0, 4); +} +static inline uint32_t MOVW_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 4); +} + +int avr_translate_MULS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t MULS_Rr(uint32_t opcode) +{ + return extract32(opcode, 0, 4); +} +static inline uint32_t MULS_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 4); +} + +int avr_translate_MULSU(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t MULSU_Rr(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t MULSU_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 3); +} + +int avr_translate_FMUL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t FMUL_Rr(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t FMUL_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 3); +} + +int avr_translate_FMULS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t FMULS_Rr(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t FMULS_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 3); +} + +int avr_translate_FMULSU(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t FMULSU_Rr(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t FMULSU_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 3); +} + +int avr_translate_CPC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t CPC_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t CPC_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_SBC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SBC_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t SBC_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_ADD(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t ADD_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t ADD_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_AND(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t AND_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t AND_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_EOR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t EOR_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t EOR_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_OR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t OR_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t OR_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_MOV(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t MOV_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t MOV_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_CPSE(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t CPSE_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t CPSE_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_CP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t CP_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t CP_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_SUB(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SUB_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t SUB_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_ADC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t ADC_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t ADC_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_CPI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t CPI_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 4); +} +static inline uint32_t CPI_Imm(uint32_t opcode) +{ + return (extract32(opcode, 8, 4) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_SBCI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SBCI_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 4); +} +static inline uint32_t SBCI_Imm(uint32_t opcode) +{ + return (extract32(opcode, 8, 4) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_ORI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t ORI_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 4); +} +static inline uint32_t ORI_Imm(uint32_t opcode) +{ + return (extract32(opcode, 8, 4) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_SUBI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SUBI_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 4); +} +static inline uint32_t SUBI_Imm(uint32_t opcode) +{ + return (extract32(opcode, 8, 4) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_ANDI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t ANDI_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 4); +} +static inline uint32_t ANDI_Imm(uint32_t opcode) +{ + return (extract32(opcode, 8, 4) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_LDDZ(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDDZ_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t LDDZ_Imm(uint32_t opcode) +{ + return (extract32(opcode, 13, 1) << 5) | + (extract32(opcode, 10, 2) << 3) | + (extract32(opcode, 0, 3)); +} + +int avr_translate_LDDY(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDDY_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t LDDY_Imm(uint32_t opcode) +{ + return (extract32(opcode, 13, 1) << 5) | + (extract32(opcode, 10, 2) << 3) | + (extract32(opcode, 0, 3)); +} + +int avr_translate_STDZ(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t STDZ_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t STDZ_Imm(uint32_t opcode) +{ + return (extract32(opcode, 13, 1) << 5) | + (extract32(opcode, 10, 2) << 3) | + (extract32(opcode, 0, 3)); +} + +int avr_translate_STDY(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t STDY_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t STDY_Imm(uint32_t opcode) +{ + return (extract32(opcode, 13, 1) << 5) | + (extract32(opcode, 10, 2) << 3) | + (extract32(opcode, 0, 3)); +} + +int avr_translate_LDS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDS_Imm(uint32_t opcode) +{ + return extract32(opcode, 0, 16); +} +static inline uint32_t LDS_Rd(uint32_t opcode) +{ + return extract32(opcode, 20, 5); +} + +int avr_translate_LDZ2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDZ2_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LDZ3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDZ3_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LPM2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LPM2_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LPMX(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LPMX_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_ELPM2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t ELPM2_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_ELPMX(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t ELPMX_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LDY2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDY2_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LDY3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDY3_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LDX1(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDX1_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LDX2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDX2_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LDX3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDX3_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_POP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t POP_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_STS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t STS_Imm(uint32_t opcode) +{ + return extract32(opcode, 0, 16); +} +static inline uint32_t STS_Rd(uint32_t opcode) +{ + return extract32(opcode, 20, 5); +} + +int avr_translate_STZ2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t STZ2_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_STZ3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t STZ3_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_XCH(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t XCH_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LAS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LAS_Rr(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LAC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LAC_Rr(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LAT(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LAT_Rr(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_STY2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t STY2_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_STY3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t STY3_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_STX1(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t STX1_Rr(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_STX2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t STX2_Rr(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_STX3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t STX3_Rr(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_PUSH(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t PUSH_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_COM(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t COM_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_NEG(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t NEG_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_SWAP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SWAP_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_INC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t INC_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_ASR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t ASR_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_LSR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LSR_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_ROR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t ROR_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_BSET(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t BSET_Bit(uint32_t opcode) +{ + return extract32(opcode, 4, 3); +} + +int avr_translate_IJMP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_EIJMP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_BCLR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t BCLR_Bit(uint32_t opcode) +{ + return extract32(opcode, 4, 3); +} + +int avr_translate_RET(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_RETI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_ICALL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_EICALL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_SLEEP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_BREAK(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_WDR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_LPM1(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_ELPM1(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_SPM(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_SPMX(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); + +int avr_translate_DEC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t DEC_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_DES(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t DES_Imm(uint32_t opcode) +{ + return extract32(opcode, 4, 4); +} + +int avr_translate_JMP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t JMP_Imm(uint32_t opcode) +{ + return (extract32(opcode, 20, 5) << 17) | + (extract32(opcode, 0, 17)); +} + +int avr_translate_CALL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t CALL_Imm(uint32_t opcode) +{ + return (extract32(opcode, 20, 5) << 17) | + (extract32(opcode, 0, 17)); +} + +int avr_translate_ADIW(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t ADIW_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 2); +} +static inline uint32_t ADIW_Imm(uint32_t opcode) +{ + return (extract32(opcode, 6, 2) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_SBIW(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SBIW_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 2); +} +static inline uint32_t SBIW_Imm(uint32_t opcode) +{ + return (extract32(opcode, 6, 2) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_CBI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t CBI_Bit(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t CBI_Imm(uint32_t opcode) +{ + return extract32(opcode, 3, 5); +} + +int avr_translate_SBIC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SBIC_Bit(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t SBIC_Imm(uint32_t opcode) +{ + return extract32(opcode, 3, 5); +} + +int avr_translate_SBI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SBI_Bit(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t SBI_Imm(uint32_t opcode) +{ + return extract32(opcode, 3, 5); +} + +int avr_translate_SBIS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SBIS_Bit(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t SBIS_Imm(uint32_t opcode) +{ + return extract32(opcode, 3, 5); +} + +int avr_translate_MUL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t MUL_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t MUL_Rr(uint32_t opcode) +{ + return (extract32(opcode, 9, 1) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_IN(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t IN_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t IN_Imm(uint32_t opcode) +{ + return (extract32(opcode, 9, 2) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_OUT(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t OUT_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} +static inline uint32_t OUT_Imm(uint32_t opcode) +{ + return (extract32(opcode, 9, 2) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_RJMP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t RJMP_Imm(uint32_t opcode) +{ + return extract32(opcode, 0, 12); +} + +int avr_translate_LDI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t LDI_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 4); +} +static inline uint32_t LDI_Imm(uint32_t opcode) +{ + return (extract32(opcode, 8, 4) << 4) | + (extract32(opcode, 0, 4)); +} + +int avr_translate_RCALL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t RCALL_Imm(uint32_t opcode) +{ + return extract32(opcode, 0, 12); +} + +int avr_translate_BRBS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t BRBS_Bit(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t BRBS_Imm(uint32_t opcode) +{ + return extract32(opcode, 3, 7); +} + +int avr_translate_BRBC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t BRBC_Bit(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t BRBC_Imm(uint32_t opcode) +{ + return extract32(opcode, 3, 7); +} + +int avr_translate_BLD(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t BLD_Bit(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t BLD_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_BST(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t BST_Bit(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t BST_Rd(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_SBRC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SBRC_Bit(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t SBRC_Rr(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + +int avr_translate_SBRS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode); +static inline uint32_t SBRS_Bit(uint32_t opcode) +{ + return extract32(opcode, 0, 3); +} +static inline uint32_t SBRS_Rr(uint32_t opcode) +{ + return extract32(opcode, 4, 5); +} + + +#endif