From patchwork Tue Jun 7 02:50:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 631301 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rNy214YHMz9t0t for ; Tue, 7 Jun 2016 13:37:45 +1000 (AEST) Received: from localhost ([::1]:46782 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bA7pn-0007r4-Ii for incoming@patchwork.ozlabs.org; Mon, 06 Jun 2016 23:37:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50783) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bA7kk-0003R8-4c for qemu-devel@nongnu.org; Mon, 06 Jun 2016 23:32:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bA7ke-0005Tw-2f for qemu-devel@nongnu.org; Mon, 06 Jun 2016 23:32:29 -0400 Received: from gate.crashing.org ([63.228.1.57]:40143) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bA7kd-0005Rd-Po; Mon, 06 Jun 2016 23:32:24 -0400 Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id u572oXdP013752; Mon, 6 Jun 2016 21:50:38 -0500 From: Benjamin Herrenschmidt To: qemu-ppc@nongnu.org Date: Tue, 7 Jun 2016 12:50:21 +1000 Message-Id: <1465267828-10326-2-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1465267828-10326-1-git-send-email-benh@kernel.crashing.org> References: <1465267828-10326-1-git-send-email-benh@kernel.crashing.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 63.228.1.57 Subject: [Qemu-devel] [PATCH 2/9] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cedric Le Goater , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The processor only uses some bits of the address and invalidates an entire congruence class. Some OSes such as Darwin and HelenOS take advantage of this and occasionally invalidate the entire TLB by just doing a series of 64 consecutive tlbie for example. Our code tries to be too smart here only invalidating a segment congruence class (ie, allowing more address bits to be relevant in the invalidation), this fails miserably on those OSes. Instead don't bother, do like ppc64 and blow the whole tlb when tlbie is executed. Signed-off-by: Benjamin Herrenschmidt --- target-ppc/mmu_helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index f5c4e69..a5e3878 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1969,6 +1969,11 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) /* XXX: this case should be optimized, * giving a mask to tlb_flush_page */ + /* This is broken, some CPUs invalidate a whole congruence + * class on an even smaller subset of bits and some OSes take + * advantage of this. Just blow the whole thing away. + */ +#if 0 tlb_flush_page(cs, addr | (0x0 << 28)); tlb_flush_page(cs, addr | (0x1 << 28)); tlb_flush_page(cs, addr | (0x2 << 28)); @@ -1985,6 +1990,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) tlb_flush_page(cs, addr | (0xD << 28)); tlb_flush_page(cs, addr | (0xE << 28)); tlb_flush_page(cs, addr | (0xF << 28)); +#else + tlb_flush(cs, 1); +#endif break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: