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[v2,06/12] tcg/mips: Add support for fence

Message ID 1464310815-13554-7-git-send-email-rth@twiddle.net
State New
Headers show

Commit Message

Richard Henderson May 27, 2016, 1 a.m. UTC 
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/mips/tcg-target.inc.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Aurelien Jarno May 30, 2016, 4:47 p.m. UTC | #1 
On 2016-05-26 18:00, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/mips/tcg-target.inc.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
> index 50e98ea..cad1d4d 100644
> --- a/tcg/mips/tcg-target.inc.c
> +++ b/tcg/mips/tcg-target.inc.c
> @@ -292,6 +292,7 @@ typedef enum {
>      OPC_JALR     = OPC_SPECIAL | 0x09,
>      OPC_MOVZ     = OPC_SPECIAL | 0x0A,
>      OPC_MOVN     = OPC_SPECIAL | 0x0B,
> +    OPC_SYNC     = OPC_SPECIAL | 0x0F,
>      OPC_MFHI     = OPC_SPECIAL | 0x10,
>      OPC_MFLO     = OPC_SPECIAL | 0x12,
>      OPC_MULT     = OPC_SPECIAL | 0x18,
> @@ -1636,6 +1637,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
>                          const_args[4], const_args[5], true);
>          break;
>  
> +    case INDEX_op_fence:
> +        tcg_out32(s, OPC_SYNC);
> +        break;
>      case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
>      case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
>      case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
> @@ -1716,6 +1720,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
>      { INDEX_op_qemu_ld_i64, { "L", "L", "lZ", "lZ" } },
>      { INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } },
>  #endif
> +
> +    { INDEX_op_fence, { } },
>      { -1 },
>  };

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

Also compiled tested, but we don't really have a way to test that so
far.
diff mbox

Patch

diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 50e98ea..cad1d4d 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -292,6 +292,7 @@  typedef enum {
     OPC_JALR     = OPC_SPECIAL | 0x09,
     OPC_MOVZ     = OPC_SPECIAL | 0x0A,
     OPC_MOVN     = OPC_SPECIAL | 0x0B,
+    OPC_SYNC     = OPC_SPECIAL | 0x0F,
     OPC_MFHI     = OPC_SPECIAL | 0x10,
     OPC_MFLO     = OPC_SPECIAL | 0x12,
     OPC_MULT     = OPC_SPECIAL | 0x18,
@@ -1636,6 +1637,9 @@  static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
                         const_args[4], const_args[5], true);
         break;
 
+    case INDEX_op_fence:
+        tcg_out32(s, OPC_SYNC);
+        break;
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
@@ -1716,6 +1720,8 @@  static const TCGTargetOpDef mips_op_defs[] = {
     { INDEX_op_qemu_ld_i64, { "L", "L", "lZ", "lZ" } },
     { INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } },
 #endif
+
+    { INDEX_op_fence, { } },
     { -1 },
 };