From patchwork Thu May 26 14:55:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 626737 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rFtKG5jMZz9sCk for ; Fri, 27 May 2016 01:26:26 +1000 (AEST) Received: from localhost ([::1]:38974 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5xB2-0008DG-Q1 for incoming@patchwork.ozlabs.org; Thu, 26 May 2016 11:26:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60232) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5x9J-0006Tx-V3 for qemu-devel@nongnu.org; Thu, 26 May 2016 11:24:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b5x9J-0004Xt-0c for qemu-devel@nongnu.org; Thu, 26 May 2016 11:24:37 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:57304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5x9G-0004Uz-FS; Thu, 26 May 2016 11:24:34 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1b5whK-00045g-UT; Thu, 26 May 2016 15:55:42 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 26 May 2016 15:55:21 +0100 Message-Id: <1464274540-19693-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464274540-19693-1-git-send-email-peter.maydell@linaro.org> References: <1464274540-19693-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH v2 03/22] target-arm: Define new arm_is_el3_or_mon() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org, Shlomo Pongratz , Shlomo Pongratz , Pavel Fedin , Shannon Zhao , Christoffer Dall Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The GICv3 system registers need to know if the CPU is AArch64 in EL3 or AArch32 in Monitor mode. This happens to be the first part of the check for arm_is_secure(), so factor it out into a new arm_is_el3_or_mon() function that the GIC can also use. Signed-off-by: Peter Maydell Reviewed-by: Shannon Zhao --- target-arm/cpu.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c741b53..2fa1f41 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1133,8 +1133,8 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env) } } -/* Return true if the processor is in secure state */ -static inline bool arm_is_secure(CPUARMState *env) +/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ +static inline bool arm_is_el3_or_mon(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_EL3)) { if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { @@ -1146,6 +1146,15 @@ static inline bool arm_is_secure(CPUARMState *env) return true; } } + return false; +} + +/* Return true if the processor is in secure state */ +static inline bool arm_is_secure(CPUARMState *env) +{ + if (arm_is_el3_or_mon(env)) { + return true; + } return arm_is_secure_below_el3(env); }