From patchwork Thu May 26 14:55:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 626725 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rFsjQ1HPbz9syq for ; Fri, 27 May 2016 00:58:50 +1000 (AEST) Received: from localhost ([::1]:38791 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5wkK-0002A5-6a for incoming@patchwork.ozlabs.org; Thu, 26 May 2016 10:58:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5whY-0007Rn-32 for qemu-devel@nongnu.org; Thu, 26 May 2016 10:55:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b5whV-000586-LV for qemu-devel@nongnu.org; Thu, 26 May 2016 10:55:55 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:57265) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5whS-00056r-Ca; Thu, 26 May 2016 10:55:50 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1b5whR-00048l-Ck; Thu, 26 May 2016 15:55:49 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 26 May 2016 15:55:32 +0100 Message-Id: <1464274540-19693-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464274540-19693-1-git-send-email-peter.maydell@linaro.org> References: <1464274540-19693-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH v2 14/22] hw/intc/arm_gicv3: Implement gicv3_set_irq() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org, Shlomo Pongratz , Shlomo Pongratz , Pavel Fedin , Shannon Zhao , Christoffer Dall Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Implement the code which updates the GIC state when an interrupt input into the GIC is asserted. Signed-off-by: Peter Maydell Reviewed-by: Shannon Zhao --- hw/intc/arm_gicv3.c | 20 +++++++++++++++++++- hw/intc/arm_gicv3_dist.c | 21 +++++++++++++++++++++ hw/intc/arm_gicv3_redist.c | 21 +++++++++++++++++++++ hw/intc/gicv3_internal.h | 2 ++ trace-events | 2 ++ 5 files changed, 65 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index e8f6766..e770409 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -311,7 +311,25 @@ static void gicv3_set_irq(void *opaque, int irq, int level) * [N+32..N+63] : PPI (internal interrupts for CPU 1 * ... */ - /* Do nothing for now */ + GICv3State *s = opaque; + + if (irq < (s->num_irq - GIC_INTERNAL)) { + /* external interrupt (SPI) */ + gicv3_dist_set_irq(s, irq + GIC_INTERNAL, level); + } else { + /* per-cpu interrupt (PPI) */ + int cpu; + + irq -= (s->num_irq - GIC_INTERNAL); + cpu = irq / GIC_INTERNAL; + irq %= GIC_INTERNAL; + assert(cpu < s->num_cpu); + /* Raising SGIs via this function would be a bug in how the board + * model wires up interrupts. + */ + assert(irq >= 16 && irq < 32); + gicv3_redist_set_irq(&s->cpu[cpu], irq, level); + } } static void arm_gicv3_post_load(GICv3State *s) diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 6ccb4d9..1634974 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -850,3 +850,24 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, } return r; } + +void gicv3_dist_set_irq(GICv3State *s, int irq, int level) +{ + /* Update distributor state for a change in an external SPI input line */ + if (level == gicv3_gicd_level_test(s, irq)) { + return; + } + + trace_gicv3_dist_set_irq(irq, level); + + gicv3_gicd_level_replace(s, irq, level); + + if (level) { + /* 0->1 edges latch the pending bit for edge-triggered interrupts */ + if (gicv3_gicd_edge_trigger_test(s, irq)) { + gicv3_gicd_pending_set(s, irq); + } + } + + gicv3_update(s, irq, 1); +} diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 18dc0c8..16b3422 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -493,3 +493,24 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, } return r; } + +void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level) +{ + /* Update redistributor state for a change in an external PPI input line */ + if (level == extract32(cs->level, irq, 1)) { + return; + } + + trace_gicv3_redist_set_irq(gicv3_redist_affid(cs), irq, level); + + cs->level = deposit32(cs->level, irq, 1, level); + + if (level) { + /* 0->1 edges latch the pending bit for edge-triggered interrupts */ + if (extract32(cs->edge_trigger, irq, 1)) { + cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 1); + } + } + + gicv3_redist_update(cs); +} diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 39196fa..8ae6d66 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -209,6 +209,8 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, unsigned size, MemTxAttrs attrs); MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, unsigned size, MemTxAttrs attrs); +void gicv3_dist_set_irq(GICv3State *s, int irq, int level); +void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level); /** * gicv3_cpuif_update: diff --git a/trace-events b/trace-events index 308d458..c006723 100644 --- a/trace-events +++ b/trace-events @@ -1922,9 +1922,11 @@ gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) "GIC gicv3_dist_badread(uint64_t offset, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " size %u secure %d: error" gicv3_dist_write(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" gicv3_dist_badwrite(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error" +gicv3_dist_set_irq(int irq, int level) "GICv3 distributor interrupt %d level changed to %d" # hw/intc/arm_gicv3_redist.c gicv3_redist_read(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 redistributor %x read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" gicv3_redist_badread(uint32_t cpu, uint64_t offset, unsigned size, bool secure) "GICv3 redistributor %x read: offset 0x%" PRIx64 " size %u secure %d: error" gicv3_redist_write(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 redistributor %x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" gicv3_redist_badwrite(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 redistributor %x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error" +gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributor %x interrupt %d level changed to %d"