From patchwork Wed May 4 06:52:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Kardashevskiy X-Patchwork-Id: 618281 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r08Cm29bMz9ssM for ; Wed, 4 May 2016 17:04:04 +1000 (AEST) Received: from localhost ([::1]:46052 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1axqql-0001Zv-0J for incoming@patchwork.ozlabs.org; Wed, 04 May 2016 03:03:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32831) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1axqkk-0006E1-Fl for qemu-devel@nongnu.org; Wed, 04 May 2016 02:57:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1axqkY-0006nE-Db for qemu-devel@nongnu.org; Wed, 04 May 2016 02:57:40 -0400 Received: from e23smtp05.au.ibm.com ([202.81.31.147]:51226) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1axqkX-0006kr-R9 for qemu-devel@nongnu.org; Wed, 04 May 2016 02:57:34 -0400 Received: from localhost by e23smtp05.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 4 May 2016 16:57:04 +1000 X-IBM-Helo: d23dlp02.au.ibm.com X-IBM-MailFrom: aik@ozlabs.ru X-IBM-RcptTo: qemu-devel@nongnu.org;qemu-ppc@nongnu.org Received: from d23relay09.au.ibm.com (d23relay09.au.ibm.com [9.185.63.181]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id 9E1C02BB0066; Wed, 4 May 2016 16:56:57 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay09.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u446udXO58589350; Wed, 4 May 2016 16:56:47 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u446tkHS028879; Wed, 4 May 2016 16:55:47 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u446tjpU027414; Wed, 4 May 2016 16:55:46 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 935B7A03CB; Wed, 4 May 2016 16:52:46 +1000 (AEST) Received: from vpl2.ozlabs.ibm.com (vpl2.ozlabs.ibm.com [10.61.141.27]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 2E4EAE3A33; Wed, 4 May 2016 16:52:36 +1000 (AEST) From: Alexey Kardashevskiy To: qemu-devel@nongnu.org Date: Wed, 4 May 2016 16:52:23 +1000 Message-Id: <1462344751-28281-12-git-send-email-aik@ozlabs.ru> X-Mailer: git-send-email 2.5.0.rc3 In-Reply-To: <1462344751-28281-1-git-send-email-aik@ozlabs.ru> References: <1462344751-28281-1-git-send-email-aik@ozlabs.ru> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16050406-0017-0000-0000-0000046C240B X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 202.81.31.147 Subject: [Qemu-devel] [PATCH qemu v16 11/19] spapr_iommu: Add root memory region X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Alexander Graf , Alex Williamson , qemu-ppc@nongnu.org, Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We are going to have multiple DMA windows at different offsets on a PCI bus. For the sake of migration, we will have as many TCE table objects pre-created as many windows supported. So we need a way to map windows dynamically onto a PCI bus when migration of a table is completed but at this stage a TCE table object does not have access to a PHB to ask it to map a DMA window backed by just migrated TCE table. This adds a "root" memory region (UINT64_MAX long) to the TCE object. This new region is mapped on a PCI bus with enabled overlapping as there will be one root MR per TCE table, each of them mapped at 0. The actual IOMMU memory region is a subregion of the root region and a TCE table enables/disables this subregion and maps it at the specific offset inside the root MR which is 1:1 mapping of a PCI address space. Signed-off-by: Alexey Kardashevskiy Reviewed-by: David Gibson Reviewed-by: Thomas Huth --- hw/ppc/spapr_iommu.c | 13 ++++++++++--- hw/ppc/spapr_pci.c | 6 +++--- include/hw/ppc/spapr.h | 2 +- 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index 52b1e0d..740836f 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -236,11 +236,16 @@ static MemoryRegionIOMMUOps spapr_iommu_ops = { static int spapr_tce_table_realize(DeviceState *dev) { sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); + Object *tcetobj = OBJECT(tcet); + char tmp[32]; tcet->fd = -1; tcet->need_vfio = false; - memory_region_init_iommu(&tcet->iommu, OBJECT(dev), &spapr_iommu_ops, - "iommu-spapr", 0); + snprintf(tmp, sizeof(tmp), "tce-root-%x", tcet->liobn); + memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX); + + snprintf(tmp, sizeof(tmp), "tce-iommu-%x", tcet->liobn); + memory_region_init_iommu(&tcet->iommu, tcetobj, &spapr_iommu_ops, tmp, 0); QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list); @@ -318,6 +323,7 @@ static void spapr_tce_table_do_enable(sPAPRTCETable *tcet) memory_region_set_size(&tcet->iommu, (uint64_t)tcet->nb_table << tcet->page_shift); + memory_region_add_subregion(&tcet->root, tcet->bus_offset, &tcet->iommu); tcet->enabled = true; } @@ -340,6 +346,7 @@ void spapr_tce_table_enable(sPAPRTCETable *tcet, static void spapr_tce_table_do_disable(sPAPRTCETable *tcet) { + memory_region_del_subregion(&tcet->root, &tcet->iommu); memory_region_set_size(&tcet->iommu, 0); spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table); @@ -371,7 +378,7 @@ static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp) MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet) { - return &tcet->iommu; + return &tcet->root; } static void spapr_tce_reset(DeviceState *dev) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index beeac06..e1b196d 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1471,13 +1471,13 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp) return; } + memory_region_add_subregion_overlap(&sphb->iommu_root, 0, + spapr_tce_get_iommu(tcet), 0); + /* Register default 32bit DMA window */ spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, nb_table); - memory_region_add_subregion(&sphb->iommu_root, tcet->bus_offset, - spapr_tce_get_iommu(tcet)); - sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); } diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index d36dda2..2026c69 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -545,7 +545,7 @@ struct sPAPRTCETable { bool bypass; bool need_vfio; int fd; - MemoryRegion iommu; + MemoryRegion root, iommu; struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ QLIST_ENTRY(sPAPRTCETable) list; };