From patchwork Fri Apr 8 20:29:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 608190 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qhWbW0rddz9t4n for ; Sat, 9 Apr 2016 06:41:59 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=u9KXUDOQ; dkim-atps=neutral Received: from localhost ([::1]:58156 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aodE5-0004XG-AY for incoming@patchwork.ozlabs.org; Fri, 08 Apr 2016 16:41:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40130) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aod2X-0004vY-RZ for qemu-devel@nongnu.org; Fri, 08 Apr 2016 16:30:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aod2W-0002Cf-46 for qemu-devel@nongnu.org; Fri, 08 Apr 2016 16:30:01 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:34409) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aod2V-0002CV-P6 for qemu-devel@nongnu.org; Fri, 08 Apr 2016 16:30:00 -0400 Received: by mail-wm0-x242.google.com with SMTP id n3so6852273wmn.1 for ; Fri, 08 Apr 2016 13:29:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=OmiiLxihsFrcwIkgRv7MimhFCQY/Mi9MIUjmh956ih4=; b=u9KXUDOQE8vZmMZOhWjdzl82sXkJz+oYmqAk4xHgtcxmMZTJziSYka3/KCVsBlst5j aUz8b9915YuoHi1q31etEAYaNTGl5U4Jy/v/1gnC5wDKUnwryFbB8Gs3ferTMikufPZD MKgPwyvebQUf4wNEU7nNe6RXz7vIIhUVm95qb+e9HO5xSXwdGrTzGMju8rDIqcgTUjUQ kuzO7jEXeIakNG1dstiNTpQmvTaKuXrY3fgwKcQhGuN5KY9NqO7H4YRaSpqEo8tdJKbN 7/8HnB2Izpq+noAJ6fVOCzK3XzAjJhlxM2dGe/Zsxu1U35k490qH/LHBbAGJxbsaUcYA SNmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=OmiiLxihsFrcwIkgRv7MimhFCQY/Mi9MIUjmh956ih4=; b=AmLpHyAl/b9H5M9I6KYNEu93STbNmrsreD6OUQ2jsSiycbvfRLXX2ou67mrZBariHu ++48W2sSxlt/XBm4p3TgS/zgEa5gdvsPjXS+B8eFq/gteWcShJCXZey14+z2g31lmown c/tVLy0D20i/ZuWQSbkNtn0CK88Zkbw+raxKOIMr76AhIc+gU1VE0QNOxHkPFB5DbHIk b6bsY4IBbq6JPyzQvmSV8MZb4GnPE+fWgAwd4EpI+hDdaai24ZND0VmsTXLIOb/PEMWl LnHuEiminJ71G7Uk8Vq7VvGnNkNYwQYw1Lf0AEOxk3/Mw1zPCJ1fO4Xrrdz8ufOs+GV/ I6Lw== X-Gm-Message-State: AD7BkJKg3NnfVCvYngq77QPN2UhdPqaiFcwDhQlZBCASMwPRtyn2dG9jGEFC8809ws2bag== X-Received: by 10.28.148.19 with SMTP id w19mr5871612wmd.10.1460147399235; Fri, 08 Apr 2016 13:29:59 -0700 (PDT) Received: from 640k.lan (94-39-141-76.adsl-ull.clienti.tiscali.it. [94.39.141.76]) by smtp.gmail.com with ESMTPSA id w10sm3849168wjz.9.2016.04.08.13.29.58 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Apr 2016 13:29:58 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 8 Apr 2016 22:29:05 +0200 Message-Id: <1460147350-7601-46-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> References: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH 45/50] mips: move CP0 functions out of cpu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These are here for historical reasons: they are needed from both gdbstub.c and op_helper.c, and the latter was compiled with fixed AREG0. It is not needed anymore, so uninline them. Signed-off-by: Paolo Bonzini --- target-mips/cpu.h | 113 ++------------------------------------------------- target-mips/helper.c | 108 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 112 insertions(+), 109 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 0636327..951267a 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -1035,115 +1035,10 @@ static inline void compute_hflags(CPUMIPSState *env) } } -#ifndef CONFIG_USER_ONLY -static inline void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global) -{ - MIPSCPU *cpu = mips_env_get_cpu(env); - - /* Flush qemu's TLB and discard all shadowed entries. */ - tlb_flush(CPU(cpu), flush_global); - env->tlb->tlb_in_use = env->tlb->nb_tlb; -} - -/* Called for updates to CP0_Status. */ -static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ - int32_t tcstatus, *tcst; - uint32_t v = cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask = ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu = (v >> CP0St_CU0) & 0xf; - mx = (v >> CP0St_MX) & 0x1; - ksu = (v >> CP0St_KSU) & 0x3; - asid = env->CP0_EntryHi & 0xff; - - tcstatus = cu << CP0TCSt_TCU0; - tcstatus |= mx << CP0TCSt_TMX; - tcstatus |= ksu << CP0TCSt_TKSU; - tcstatus |= asid; - - if (tc == cpu->current_tc) { - tcst = &cpu->active_tc.CP0_TCStatus; - } else { - tcst = &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &= ~mask; - *tcst |= tcstatus; - compute_hflags(cpu); -} - -static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask = env->CP0_Status_rw_bitmask; - target_ulong old = env->CP0_Status; - - if (env->insn_flags & ISA_MIPS32R6) { - bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux = (1 << CP0St_KX) & val; - ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ - ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ - val = (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { - mask &= ~(3 << CP0St_KSU); - } - mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } - - env->CP0_Status = (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled */ - cpu_mips_tlb_flush(env, 1); - } -#endif - if (env->CP0_Config3 & (1 << CP0C3_MT)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); - } -} - -static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask = 0x00C00300; - uint32_t old = env->CP0_Cause; - int i; - - if (env->insn_flags & ISA_MIPS32R2) { - mask |= 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS32R6) { - mask &= ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); - } - } - - /* Set/reset software interrupts */ - for (i = 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); - } - } -} -#endif +void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global); +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, int error_code, uintptr_t pc); diff --git a/target-mips/helper.c b/target-mips/helper.c index 0fabfec..ac5771e 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -221,6 +221,114 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, } return ret; } + +void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global) +{ + MIPSCPU *cpu = mips_env_get_cpu(env); + + /* Flush qemu's TLB and discard all shadowed entries. */ + tlb_flush(CPU(cpu), flush_global); + env->tlb->tlb_in_use = env->tlb->nb_tlb; +} + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v = cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask = ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu = (v >> CP0St_CU0) & 0xf; + mx = (v >> CP0St_MX) & 0x1; + ksu = (v >> CP0St_KSU) & 0x3; + asid = env->CP0_EntryHi & 0xff; + + tcstatus = cu << CP0TCSt_TCU0; + tcstatus |= mx << CP0TCSt_TMX; + tcstatus |= ksu << CP0TCSt_TKSU; + tcstatus |= asid; + + if (tc == cpu->current_tc) { + tcst = &cpu->active_tc.CP0_TCStatus; + } else { + tcst = &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &= ~mask; + *tcst |= tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask = env->CP0_Status_rw_bitmask; + target_ulong old = env->CP0_Status; + + if (env->insn_flags & ISA_MIPS32R6) { + bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux = (1 << CP0St_KX) & val; + ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ + ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ + val = (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { + mask &= ~(3 << CP0St_KSU); + } + mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status = (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled */ + cpu_mips_tlb_flush(env, 1); + } +#endif + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask = 0x00C00300; + uint32_t old = env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS32R2) { + mask |= 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS32R6) { + mask &= ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i = 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); + } + } +} #endif static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,