From patchwork Thu Apr 7 15:53:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sergey.fedorov@linaro.org X-Patchwork-Id: 607475 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qgnHt6vTjz9sBm for ; Fri, 8 Apr 2016 01:55:54 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b=X+EGpPl6; dkim-atps=neutral Received: from localhost ([::1]:50822 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aoCHg-0002dA-3V for incoming@patchwork.ozlabs.org; Thu, 07 Apr 2016 11:55:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56743) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aoCGv-0001BD-Q2 for qemu-devel@nongnu.org; Thu, 07 Apr 2016 11:55:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aoCGp-0002lH-Rl for qemu-devel@nongnu.org; Thu, 07 Apr 2016 11:55:05 -0400 Received: from mail-lf0-x230.google.com ([2a00:1450:4010:c07::230]:35592) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aoCGp-0002l3-Ea for qemu-devel@nongnu.org; Thu, 07 Apr 2016 11:54:59 -0400 Received: by mail-lf0-x230.google.com with SMTP id c126so60346336lfb.2 for ; Thu, 07 Apr 2016 08:54:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bGT9EcK9xF8IyF+z6cP4Txpjq97wqvZuVUNs3kfwYUU=; b=X+EGpPl6zT41pvL7XGgKQGGdKKD8P8FYDOIxuYB0k5eBnMaYOFbf7rNKN42USWGfEv yEgu82kHf3JsZdNlKpUNYkt0u5Orrg7hHjVCELmZoZIJAM1YvL7lOUb2vPUIDXqxInnJ 7+jGE0HCy+4GRHv/T065k699kVDqemEVVfl9w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bGT9EcK9xF8IyF+z6cP4Txpjq97wqvZuVUNs3kfwYUU=; b=c7ucLUxqSR+gD290BdLolD6x9tp+OXqyzqEXmMN5LZtlif69eI0/Rd2tGMd+S45f6f nYVe4X97YDCHQ7+M/M9ozc0H38tnku+clQ9mW4ve102NCzMIEPw09EANhykGyDOQdOCE kiTfC7Y9VZhTan40LLnP/K1/Wlfju1SuhFCzQkHznhjFPESRVkoZ64rxEpA1MOOE1WmU YCA3YnOKwc1ji/6MwoURj5x9MQXLQZQCpUjwK5MM0nErJDyl84Gx7e1rGpFuMctbmE3f BzJCJ87fODuKpNwiCY6iNoa96xbZOgzLWZ5jWhGRSsWuxzJsCnTKY/YgleM45C81Pmyt G0Ow== X-Gm-Message-State: AD7BkJJMJeK+GOtldGYfIK0YNFJsam1XXoL2mG27CnVoOFMkvbXFy/Cwscz9toyiqSsJggwO X-Received: by 10.25.29.211 with SMTP id d202mr1708375lfd.92.1460044498616; Thu, 07 Apr 2016 08:54:58 -0700 (PDT) Received: from localhost.localdomain ([195.91.132.170]) by smtp.gmail.com with ESMTPSA id p195sm1316255lfd.11.2016.04.07.08.54.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Apr 2016 08:54:57 -0700 (PDT) From: Sergey Fedorov To: qemu-devel@nongnu.org Date: Thu, 7 Apr 2016 18:53:43 +0300 Message-Id: <1460044433-19282-2-git-send-email-sergey.fedorov@linaro.org> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1460044433-19282-1-git-send-email-sergey.fedorov@linaro.org> References: <1460044433-19282-1-git-send-email-sergey.fedorov@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:4010:c07::230 Cc: Peter Crosthwaite , Stefan Weil , Paolo Bonzini , Sergey Fedorov , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Subject: [Qemu-devel] [PATCH 01/11] tci: Fix build regression X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Stefan Weil Commit d38ea87ac54af64ef611de434d07c12dc0399216 cleaned the include statements which resulted in a wrong order of assert.h and the definition of NDEBUG in tci.c. Normally NDEBUG modifies the definition of the assert macro, but here this definition comes too late which results in a failing build. To fix this, a new macro tci_assert which depends on CONFIG_DEBUG_TCG is introduced. Only builds with CONFIG_DEBUG_TCG will use assertions. Even in this case, it is still possible to disable assertions by defining NDEBUG via compiler settings. Signed-off-by: Stefan Weil --- tci.c | 41 ++++++++++++++++++++++------------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/tci.c b/tci.c index 7cbb39ed4b6a..82705fe77295 100644 --- a/tci.c +++ b/tci.c @@ -1,7 +1,7 @@ /* * Tiny Code Interpreter for QEMU * - * Copyright (c) 2009, 2011 Stefan Weil + * Copyright (c) 2009, 2011, 2016 Stefan Weil * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,9 +19,12 @@ #include "qemu/osdep.h" -/* Defining NDEBUG disables assertions (which makes the code faster). */ -#if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG) -# define NDEBUG +/* Enable TCI assertions only when debugging TCG (and without NDEBUG defined). + * Without assertions, the interpreter runs much faster. */ +#if defined(CONFIG_DEBUG_TCG) +# define tci_assert(cond) assert(cond) +#else +# define tci_assert(cond) ((void)0) #endif #include "qemu-common.h" @@ -56,7 +59,7 @@ static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS]; static tcg_target_ulong tci_read_reg(TCGReg index) { - assert(index < ARRAY_SIZE(tci_reg)); + tci_assert(index < ARRAY_SIZE(tci_reg)); return tci_reg[index]; } @@ -105,9 +108,9 @@ static uint64_t tci_read_reg64(TCGReg index) static void tci_write_reg(TCGReg index, tcg_target_ulong value) { - assert(index < ARRAY_SIZE(tci_reg)); - assert(index != TCG_AREG0); - assert(index != TCG_REG_CALL_STACK); + tci_assert(index < ARRAY_SIZE(tci_reg)); + tci_assert(index != TCG_AREG0); + tci_assert(index != TCG_REG_CALL_STACK); tci_reg[index] = value; } @@ -325,7 +328,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr) static tcg_target_ulong tci_read_label(uint8_t **tb_ptr) { tcg_target_ulong label = tci_read_i(tb_ptr); - assert(label != 0); + tci_assert(label != 0); return label; } @@ -468,11 +471,11 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tci_reg[TCG_AREG0] = (tcg_target_ulong)env; tci_reg[TCG_REG_CALL_STACK] = sp_value; - assert(tb_ptr); + tci_assert(tb_ptr); for (;;) { TCGOpcode opc = tb_ptr[0]; -#if !defined(NDEBUG) +#if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG) uint8_t op_size = tb_ptr[1]; uint8_t *old_code_ptr = tb_ptr; #endif @@ -525,7 +528,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) break; case INDEX_op_br: label = tci_read_label(&tb_ptr); - assert(tb_ptr == old_code_ptr + op_size); + tci_assert(tb_ptr == old_code_ptr + op_size); tb_ptr = (uint8_t *)label; continue; case INDEX_op_setcond_i32: @@ -600,7 +603,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t0 = tci_read_r32(&tb_ptr); t1 = tci_read_r(&tb_ptr); t2 = tci_read_s32(&tb_ptr); - assert(t1 != sp_value || (int32_t)t2 < 0); + tci_assert(t1 != sp_value || (int32_t)t2 < 0); *(uint32_t *)(t1 + t2) = t0; break; @@ -725,7 +728,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { - assert(tb_ptr == old_code_ptr + op_size); + tci_assert(tb_ptr == old_code_ptr + op_size); tb_ptr = (uint8_t *)label; continue; } @@ -751,7 +754,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare64(tmp64, v64, condition)) { - assert(tb_ptr == old_code_ptr + op_size); + tci_assert(tb_ptr == old_code_ptr + op_size); tb_ptr = (uint8_t *)label; continue; } @@ -885,7 +888,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t0 = tci_read_r64(&tb_ptr); t1 = tci_read_r(&tb_ptr); t2 = tci_read_s32(&tb_ptr); - assert(t1 != sp_value || (int32_t)t2 < 0); + tci_assert(t1 != sp_value || (int32_t)t2 < 0); *(uint64_t *)(t1 + t2) = t0; break; @@ -992,7 +995,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { - assert(tb_ptr == old_code_ptr + op_size); + tci_assert(tb_ptr == old_code_ptr + op_size); tb_ptr = (uint8_t *)label; continue; } @@ -1087,7 +1090,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) break; case INDEX_op_goto_tb: t0 = tci_read_i32(&tb_ptr); - assert(tb_ptr == old_code_ptr + op_size); + tci_assert(tb_ptr == old_code_ptr + op_size); tb_ptr += (int32_t)t0; continue; case INDEX_op_qemu_ld_i32: @@ -1234,7 +1237,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) TODO(); break; } - assert(tb_ptr == old_code_ptr + op_size); + tci_assert(tb_ptr == old_code_ptr + op_size); } exit: return next_tb;