From patchwork Wed Mar 30 08:50:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 603264 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qZhNB3h1lz9snm for ; Wed, 30 Mar 2016 19:56:58 +1100 (AEDT) Received: from localhost ([::1]:52586 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBvs-00064o-Ob for incoming@patchwork.ozlabs.org; Wed, 30 Mar 2016 04:56:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34323) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpx-00033n-TO for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alBpr-0001sK-Im for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:49 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:17847) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpr-0001s9-9o for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:43 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 7F9C79FD9EAF for ; Wed, 30 Mar 2016 09:50:40 +0100 (IST) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 30 Mar 2016 09:50:41 +0100 From: Leon Alrae To: Date: Wed, 30 Mar 2016 09:50:00 +0100 Message-ID: <1459327802-5102-20-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> References: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL v2 19/21] hw/mips/cps: enable ITU for multithreading processors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Make ITU available in the system if CPU supports multithreading and is part of CPS. Signed-off-by: Leon Alrae --- hw/mips/cps.c | 32 ++++++++++++++++++++++++++++++++ include/hw/mips/cps.h | 2 ++ 2 files changed, 34 insertions(+) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index d46547c..1bafbbb 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -22,6 +22,7 @@ #include "hw/mips/cps.h" #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" +#include "sysemu/kvm.h" qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) { @@ -56,6 +57,14 @@ static void main_cpu_reset(void *opaque) cs->halted = 1; } +static bool cpu_mips_itu_supported(CPUMIPSState *env) +{ + bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || + (env->CP0_Config3 & (1 << CP0C3_MT)); + + return is_mt && !kvm_enabled(); +} + static void mips_cps_realize(DeviceState *dev, Error **errp) { MIPSCPSState *s = MIPS_CPS(dev); @@ -64,6 +73,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) int i; Error *err = NULL; target_ulong gcr_base; + bool itu_present = false; for (i = 0; i < s->num_vp; i++) { cpu = cpu_mips_init(s->cpu_model); @@ -76,12 +86,34 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Init internal devices */ cpu_mips_irq_init_cpu(env); cpu_mips_clock_init(env); + if (cpu_mips_itu_supported(env)) { + itu_present = true; + /* Attach ITC Tag to the VP */ + env->itc_tag = mips_itu_get_tag_region(&s->itu); + } qemu_register_reset(main_cpu_reset, cpu); } cpu = MIPS_CPU(first_cpu); env = &cpu->env; + /* Inter-Thread Communication Unit */ + if (itu_present) { + object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU); + qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default()); + + object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); + object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err); + object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); + } + /* Cluster Power Controller */ object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC); qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default()); diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 88be765..4dbae9c 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -23,6 +23,7 @@ #include "hw/sysbus.h" #include "hw/misc/mips_cmgcr.h" #include "hw/misc/mips_cpc.h" +#include "hw/misc/mips_itu.h" #define TYPE_MIPS_CPS "mips-cps" #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS) @@ -37,6 +38,7 @@ typedef struct MIPSCPSState { MemoryRegion container; MIPSGCRState gcr; MIPSCPCState cpc; + MIPSITUState itu; } MIPSCPSState; qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);