From patchwork Wed Mar 30 08:49:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 603261 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qZhKz33spz9sD3 for ; Wed, 30 Mar 2016 19:55:03 +1100 (AEDT) Received: from localhost ([::1]:52562 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBu1-0002c6-MQ for incoming@patchwork.ozlabs.org; Wed, 30 Mar 2016 04:55:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34205) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpq-0002p8-DK for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alBpp-0001rI-CJ for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:42 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:60873) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpp-0001qx-6P for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:41 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 4CEBBFA24E426 for ; Wed, 30 Mar 2016 09:50:38 +0100 (IST) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 30 Mar 2016 09:50:39 +0100 From: Leon Alrae To: Date: Wed, 30 Mar 2016 09:49:56 +0100 Message-ID: <1459327802-5102-16-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> References: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL v2 15/21] hw/mips: implement ITC Storage - P/V Sync and Try Views X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org P/V Synchronized and Try Views can be used to access Semaphore cells. Load returns current value and post-decrements the value in the cell (until it reaches zero). Stores increment the value (until it saturates at 0xFFFF). P/V Synchronized View causes the issuing thread to block on read if value is 0. P/V Try View does not block the thread, it returns 0 in this case. Cell's Empty and Full bits are not modified. Trap bit (i.e. Gating Storage exceptions) not implemented. Signed-off-by: Leon Alrae --- hw/misc/mips_itu.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 24a1474..595d2d2 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -33,6 +33,8 @@ #define ITC_SEMAPH_NUM_MAX 16 #define ITC_AM1_NUMENTRIES_OFS 20 +#define ITC_CELL_PV_MAX_VAL 0xFFFF + #define ITC_CELL_TAG_FIFO_DEPTH 28 #define ITC_CELL_TAG_FIFO_PTR 18 #define ITC_CELL_TAG_FIFO 17 @@ -284,6 +286,60 @@ static void view_ef_try_write(ITCStorageCell *c, uint64_t val) view_ef_common_write(c, val, false); } +/* ITC P/V View */ + +static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking) +{ + uint64_t ret = c->data[0]; + + if (c->tag.FIFO) { + return 0; + } + + if (c->data[0] > 0) { + c->data[0]--; + } else if (blocking) { + block_thread_and_exit(c); + } + + return ret; +} + +static uint64_t view_pv_sync_read(ITCStorageCell *c) +{ + return view_pv_common_read(c, true); +} + +static uint64_t view_pv_try_read(ITCStorageCell *c) +{ + return view_pv_common_read(c, false); +} + +static inline void view_pv_common_write(ITCStorageCell *c) +{ + if (c->tag.FIFO) { + return; + } + + if (c->data[0] < ITC_CELL_PV_MAX_VAL) { + c->data[0]++; + } + + if (c->blocked_threads) { + wake_blocked_threads(c); + } +} + +static void view_pv_sync_write(ITCStorageCell *c) +{ + view_pv_common_write(c); +} + +static void view_pv_try_write(ITCStorageCell *c) +{ + view_pv_common_write(c); +} + static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) { MIPSITUState *s = (MIPSITUState *)opaque; @@ -301,6 +357,12 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) case ITCVIEW_EF_TRY: ret = view_ef_try_read(cell); break; + case ITCVIEW_PV_SYNC: + ret = view_pv_sync_read(cell); + break; + case ITCVIEW_PV_TRY: + ret = view_pv_try_read(cell); + break; default: qemu_log_mask(LOG_GUEST_ERROR, "itc_storage_read: Bad ITC View %d\n", (int)view); @@ -327,6 +389,12 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data, case ITCVIEW_EF_TRY: view_ef_try_write(cell, data); break; + case ITCVIEW_PV_SYNC: + view_pv_sync_write(cell); + break; + case ITCVIEW_PV_TRY: + view_pv_try_write(cell); + break; default: qemu_log_mask(LOG_GUEST_ERROR, "itc_storage_write: Bad ITC View %d\n", (int)view);