From patchwork Wed Mar 30 08:49:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 603256 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qZhHh4ByPz9snm for ; Wed, 30 Mar 2016 19:53:04 +1100 (AEDT) Received: from localhost ([::1]:52542 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBs6-0007Pl-SK for incoming@patchwork.ozlabs.org; Wed, 30 Mar 2016 04:53:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34178) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpp-0002nQ-Ec for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alBpo-0001qa-Db for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:41 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:58326) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpo-0001qS-7j for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:40 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 4732CC2A327BD for ; Wed, 30 Mar 2016 09:50:37 +0100 (IST) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 30 Mar 2016 09:50:38 +0100 From: Leon Alrae To: Date: Wed, 30 Mar 2016 09:49:54 +0100 Message-ID: <1459327802-5102-14-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> References: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL v2 13/21] hw/mips: implement ITC Storage - Control View X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Control view is used to access the ITC Storage Cell Tags. It never causes the issuing thread to block. Guest can empty the FIFO cell by setting Empty bit to 1. Signed-off-by: Leon Alrae --- hw/misc/mips_itu.c | 104 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 330db1a..120b14c 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -33,12 +33,28 @@ #define ITC_SEMAPH_NUM_MAX 16 #define ITC_AM1_NUMENTRIES_OFS 20 +#define ITC_CELL_TAG_FIFO_DEPTH 28 +#define ITC_CELL_TAG_FIFO_PTR 18 +#define ITC_CELL_TAG_FIFO 17 +#define ITC_CELL_TAG_T 16 +#define ITC_CELL_TAG_F 1 +#define ITC_CELL_TAG_E 0 + #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL #define ITC_AM0_EN_MASK 0x1 #define ITC_AM1_ADDR_MASK_MASK 0x1FC00 #define ITC_AM1_ENTRY_GRAIN_MASK 0x7 +typedef enum ITCView { + ITCVIEW_BYPASS = 0, + ITCVIEW_CONTROL = 1, + ITCVIEW_EF_SYNC = 2, + ITCVIEW_EF_TRY = 3, + ITCVIEW_PV_SYNC = 4, + ITCVIEW_PV_TRY = 5 +} ITCView; + MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu) { return &itu->tag_io; @@ -120,7 +136,95 @@ static inline uint32_t get_num_cells(MIPSITUState *s) return s->num_fifo + s->num_semaphores; } +static inline ITCView get_itc_view(hwaddr addr) +{ + return (addr >> 3) & 0xf; +} + +static inline int get_cell_stride_shift(const MIPSITUState *s) +{ + /* Minimum interval (for EntryGain = 0) is 128 B */ + return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); +} + +static inline ITCStorageCell *get_cell(MIPSITUState *s, + hwaddr addr) +{ + uint32_t cell_idx = addr >> get_cell_stride_shift(s); + uint32_t num_cells = get_num_cells(s); + + if (cell_idx >= num_cells) { + cell_idx = num_cells - 1; + } + + return &s->cell[cell_idx]; +} + +/* ITC Control View */ + +static inline uint64_t view_control_read(ITCStorageCell *c) +{ + return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) | + (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) | + (c->tag.FIFO << ITC_CELL_TAG_FIFO) | + (c->tag.T << ITC_CELL_TAG_T) | + (c->tag.E << ITC_CELL_TAG_E) | + (c->tag.F << ITC_CELL_TAG_F); +} + +static inline void view_control_write(ITCStorageCell *c, uint64_t val) +{ + c->tag.T = (val >> ITC_CELL_TAG_T) & 1; + c->tag.E = (val >> ITC_CELL_TAG_E) & 1; + c->tag.F = (val >> ITC_CELL_TAG_F) & 1; + + if (c->tag.E) { + c->tag.FIFOPtr = 0; + } +} + +static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) +{ + MIPSITUState *s = (MIPSITUState *)opaque; + ITCStorageCell *cell = get_cell(s, addr); + ITCView view = get_itc_view(addr); + uint64_t ret = -1; + + switch (view) { + case ITCVIEW_CONTROL: + ret = view_control_read(cell); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "itc_storage_read: Bad ITC View %d\n", (int)view); + break; + } + + return ret; +} + +static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) +{ + MIPSITUState *s = (MIPSITUState *)opaque; + ITCStorageCell *cell = get_cell(s, addr); + ITCView view = get_itc_view(addr); + + switch (view) { + case ITCVIEW_CONTROL: + view_control_write(cell, data); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "itc_storage_write: Bad ITC View %d\n", (int)view); + break; + } + +} + static const MemoryRegionOps itc_storage_ops = { + .read = itc_storage_read, + .write = itc_storage_write, .endianness = DEVICE_NATIVE_ENDIAN, };