From patchwork Wed Mar 16 17:57:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 598577 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qQK4b4bn9z9s5g for ; Thu, 17 Mar 2016 04:59:27 +1100 (AEDT) Received: from localhost ([::1]:57965 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1agFjB-0007i4-R7 for incoming@patchwork.ozlabs.org; Wed, 16 Mar 2016 13:59:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48225) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1agFhN-0003pV-KS for qemu-devel@nongnu.org; Wed, 16 Mar 2016 13:57:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1agFhJ-0005Bl-KY for qemu-devel@nongnu.org; Wed, 16 Mar 2016 13:57:33 -0400 Received: from e06smtp17.uk.ibm.com ([195.75.94.113]:45217) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1agFhJ-0005Ax-AG for qemu-devel@nongnu.org; Wed, 16 Mar 2016 13:57:29 -0400 Received: from localhost by e06smtp17.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 16 Mar 2016 17:57:27 -0000 Received: from d06dlp03.portsmouth.uk.ibm.com (9.149.20.15) by e06smtp17.uk.ibm.com (192.168.101.147) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Wed, 16 Mar 2016 17:57:25 -0000 X-IBM-Helo: d06dlp03.portsmouth.uk.ibm.com X-IBM-MailFrom: clg@fr.ibm.com X-IBM-RcptTo: qemu-devel@nongnu.org;qemu-ppc@nongnu.org Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id 160541B0806B; Wed, 16 Mar 2016 17:57:54 +0000 (GMT) Received: from d06av03.portsmouth.uk.ibm.com (d06av03.portsmouth.uk.ibm.com [9.149.37.213]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u2GHvPWv3211654; Wed, 16 Mar 2016 17:57:25 GMT Received: from d06av03.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av03.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u2GHvNR2011085; Wed, 16 Mar 2016 11:57:24 -0600 Received: from hermes.ibm.com (icon-9-164-156-114.megacenter.de.ibm.com [9.164.156.114]) by d06av03.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u2GHvMLY011043; Wed, 16 Mar 2016 11:57:22 -0600 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 16 Mar 2016 18:57:05 +0100 Message-Id: <1458151025-9399-1-git-send-email-clg@fr.ibm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1458134034-32500-9-git-send-email-clg@fr.ibm.com> References: <1458134034-32500-9-git-send-email-clg@fr.ibm.com> MIME-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16031617-0005-0000-0000-00000AEA4B13 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.75.94.113 Cc: Thomas Huth , Cedric Le Goater , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH v3 08/10] ppc: Add POWER8 IAMR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Benjamin Herrenschmidt With appropriate AMR-like masks. Not actually used by the translation logic at that point Signed-off-by: Benjamin Herrenschmidt [clg: changed spr_register_hv(SPR_IAMR) to spr_register_kvm_hv(SPR_IAMR) changed gen_spr_amr() prototype ] Signed-off-by: Cédric Le Goater Reviewed-by: Thomas Huth Reviewed-by: David Gibson --- Changes since v2: - fixed has_iamr condition in gen_spr_amr() target-ppc/cpu.h | 1 + target-ppc/translate_init.c | 41 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 167c73f863b3..a3c4fb112a3e 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1360,6 +1360,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch) #define SPR_BOOKE_CSRR0 (0x03A) #define SPR_BOOKE_CSRR1 (0x03B) #define SPR_BOOKE_DEAR (0x03D) +#define SPR_IAMR (0x03D) #define SPR_BOOKE_ESR (0x03E) #define SPR_BOOKE_IVPR (0x03F) #define SPR_MPC_EIE (0x050) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 4514188ff07c..c78b532e8f3c 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -1126,9 +1126,39 @@ static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) tcg_temp_free(t1); tcg_temp_free(t2); } + +static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + + /* Note, the HV=1 case is handled earlier by simply using + * spr_write_generic for HV mode in the SPR table + */ + + /* Build insertion mask into t1 based on context */ + gen_load_spr(t1, SPR_AMOR); + + /* Mask new bits into t2 */ + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); + + /* Load AMR and clear new bits in t0 */ + gen_load_spr(t0, SPR_IAMR); + tcg_gen_andc_tl(t0, t0, t1); + + /* Or'in new bits and write it out */ + tcg_gen_or_tl(t0, t0, t2); + gen_store_spr(SPR_IAMR, t0); + spr_store_dump_spr(SPR_IAMR); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); +} #endif /* CONFIG_USER_ONLY */ -static void gen_spr_amr (CPUPPCState *env) +static void gen_spr_amr(CPUPPCState *env, bool has_iamr) { #ifndef CONFIG_USER_ONLY /* Virtual Page Class Key protection */ @@ -1154,6 +1184,13 @@ static void gen_spr_amr (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0); + if (has_iamr) { + spr_register_kvm_hv(env, SPR_IAMR, "IAMR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_iamr, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_IAMR, 0); + } #endif /* !CONFIG_USER_ONLY */ } #endif /* TARGET_PPC64 */ @@ -8000,7 +8037,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) case BOOK3S_CPU_POWER7: case BOOK3S_CPU_POWER8: gen_spr_book3s_ids(env); - gen_spr_amr(env); + gen_spr_amr(env, version >= BOOK3S_CPU_POWER8); gen_spr_book3s_purr(env); env->ci_large_pages = true; break;