From patchwork Tue Mar 1 14:09:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 590539 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6EA731400A0 for ; Wed, 2 Mar 2016 01:10:00 +1100 (AEDT) Received: from localhost ([::1]:49819 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aakzu-0004T1-Gl for incoming@patchwork.ozlabs.org; Tue, 01 Mar 2016 09:09:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36545) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aakzZ-0004Av-6g for qemu-devel@nongnu.org; Tue, 01 Mar 2016 09:09:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aakzV-0004mI-0C for qemu-devel@nongnu.org; Tue, 01 Mar 2016 09:09:37 -0500 Received: from mx1.redhat.com ([209.132.183.28]:51410) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aakzU-0004m7-QV for qemu-devel@nongnu.org; Tue, 01 Mar 2016 09:09:32 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (Postfix) with ESMTPS id 89549C00F23C; Tue, 1 Mar 2016 14:09:32 +0000 (UTC) Received: from donizetti.redhat.com (ovpn-112-77.ams2.redhat.com [10.36.112.77]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u21E9U57017315; Tue, 1 Mar 2016 09:09:31 -0500 From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 1 Mar 2016 15:09:30 +0100 Message-Id: <1456841370-14602-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: hpoussin@reactos.org Subject: [Qemu-devel] [PATCH] target-i386: fix interrupt shadow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The handling of the interrupt shadow is subtle. QEMU's check to stop the interrupt shadow needs to check the state after the _penultimate_ instruction. Because the interrupt shadow is only enabled at the end of a translation block, and it makes the next, the state at the penultimate instruction is stored in the current translation block's flags. Fix gen_eob to check it correctly. This fixes Windows XP. Reported-by: Hervé Poussineau Fixes: 7f0b7141b4c7deab51efd8ee1e83eab2d9b7a9ea Signed-off-by: Paolo Bonzini Tested-by: Hervé Poussineau --- target-i386/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 9171929..0ed2ee9 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2424,7 +2424,14 @@ static void gen_bnd_jmp(DisasContext *s) static void gen_eob(DisasContext *s) { gen_update_cc_op(s); - gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); + /* If the last instruction of the previous block inhibited IRQ, + * re-enable interrupts here. The interrupt shadow never lasts + * more than one instruction, hence interrupts must always be + * re-enabled by the one-instruction tb with HF_INHIBIT_IRQ_MASK. + */ + if ((s->tb->flags & HF_INHIBIT_IRQ_MASK) != 0) { + gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); + } if (s->tb->flags & HF_RF_MASK) { gen_helper_reset_rf(cpu_env); } @@ -5173,8 +5180,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_pop_update(s, ot); if (reg == R_SS) { /* if reg == SS, inhibit interrupts/trace. */ - /* If several instructions disable interrupts, only the - _first_ does it */ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); s->tf = 0; } @@ -5240,8 +5245,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_movl_seg_T0(s, reg); if (reg == R_SS) { /* if reg == SS, inhibit interrupts/trace */ - /* If several instructions disable interrupts, only the - _first_ does it */ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); s->tf = 0; } @@ -6778,8 +6781,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_sti: gen_helper_sti(cpu_env); /* interruptions are enabled only the first insn after sti */ - /* If several instructions disable interrupts, only the - _first_ does it */ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); /* give a chance to handle pending irqs */ gen_jmp_im(s->pc - s->cs_base);