From patchwork Tue Feb 23 21:11:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 587080 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 87E0014076E for ; Wed, 24 Feb 2016 08:21:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=e9VelYy3; dkim-atps=neutral Received: from localhost ([::1]:59993 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYKOM-0003YS-0L for incoming@patchwork.ozlabs.org; Tue, 23 Feb 2016 16:21:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51016) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYKGC-0006Hy-SR for qemu-devel@nongnu.org; Tue, 23 Feb 2016 16:12:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aYKG6-0001M1-Pz for qemu-devel@nongnu.org; Tue, 23 Feb 2016 16:12:44 -0500 Received: from mail-qg0-x236.google.com ([2607:f8b0:400d:c04::236]:34201) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYKG6-0001Lr-Jw for qemu-devel@nongnu.org; Tue, 23 Feb 2016 16:12:38 -0500 Received: by mail-qg0-x236.google.com with SMTP id b67so147363033qgb.1 for ; Tue, 23 Feb 2016 13:12:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=sAJZ6h3v5DoEKi2Nm7TGjM9E46zSUCG56L4OPOWUrHo=; b=e9VelYy3Bf6ap2F29ZnvF3d3yKrnT4qyL/qqge0Iopv07QVNzriKHtaf1lAgSbUDuG uWnTqEbe4HHrwqVWe+j55jrytqF+0JJwog+4GVOf7ZteJQV3+nC6xG4G++vBTWsOowHY qFmz+F4W0mZl88g+VVrlT4jsTwhjRYQ3WmIkhCk8ph9cu/ALnU6dOJhSHRqP/n5iUFNW VBXayLiYepr29VrzxEwL+7IrVSbzxOwhXtC7S4JDp/uyXireCJHiq6KV/jVKurLpKqEr vUiILDjw6vccS6Uefj8GfKd13gEDmZbF6YkJYFtZ1xU8fMiQ2vFJSQz+EEgMmh93HUxr dC+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=sAJZ6h3v5DoEKi2Nm7TGjM9E46zSUCG56L4OPOWUrHo=; b=WwyBa9G8PemQ5RoFdp6mbQoZE4M1qrADuZt7XBDLez8+3rjcN8RipR6goMOr+OZYpI Fm1KyLqkviu0+5qtJePV1qGGzsoOi9Y8/sRgDEunMo1v5RRvrmJLCVMBr9kZLJeccv1G yz0bYDfZgyZh6979yo5nW7bA88wVg1/wnDiPAZU29FI3BNWPSTraemfO7PZiNLb5cmqx sB2LPcbNG+qYEd3eunFVky5wPo0Eq0sq6tmOiBR1VUhFCX+TAHH9SEMRaAzWv2ZWd4Hc /JId5aw1/p1Woa3VqVUzUoBmiUJBCGStwU2A8ce076nwCHwWX9ut9SQkqnxJxQs4ErCo kyAw== X-Gm-Message-State: AG10YOQjaecFAjXYrRB4BMDJ2pf6UkGjihZ76IO1skln2hLmOJAz0El/2fCmd6ePXYxLqw== X-Received: by 10.140.44.38 with SMTP id f35mr44633141qga.49.1456261958067; Tue, 23 Feb 2016 13:12:38 -0800 (PST) Received: from anchor.com (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by smtp.gmail.com with ESMTPSA id 200sm12775546qhm.47.2016.02.23.13.12.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Feb 2016 13:12:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Feb 2016 13:11:55 -0800 Message-Id: <1456261920-29900-20-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1456261920-29900-1-git-send-email-rth@twiddle.net> References: <1456261920-29900-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c04::236 Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [Qemu-devel] [PATCH v2 19/24] target-sparc: Directly implement block and short ldf/stf asis X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-sparc/translate.c | 106 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 0621c06..017c3c1 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -1977,6 +1977,8 @@ typedef enum { GET_ASI_EXCP, GET_ASI_DIRECT, GET_ASI_DTWINX, + GET_ASI_BLOCK, + GET_ASI_SHORT, } ASIType; typedef struct { @@ -2043,18 +2045,32 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop) case ASI_AIUPL: /* As if user primary LE */ case ASI_TWINX_AIUP: case ASI_TWINX_AIUP_L: + case ASI_BLK_AIUP_4V: + case ASI_BLK_AIUP_L_4V: + case ASI_BLK_AIUP: + case ASI_BLK_AIUPL: mem_idx = MMU_USER_IDX; break; case ASI_AIUS: /* As if user secondary */ case ASI_AIUSL: /* As if user secondary LE */ case ASI_TWINX_AIUS: case ASI_TWINX_AIUS_L: + case ASI_BLK_AIUS_4V: + case ASI_BLK_AIUS_L_4V: + case ASI_BLK_AIUS: + case ASI_BLK_AIUSL: mem_idx = MMU_USER_SECONDARY_IDX; break; case ASI_S: /* Secondary */ case ASI_SL: /* Secondary LE */ case ASI_TWINX_S: case ASI_TWINX_SL: + case ASI_BLK_S: + case ASI_BLK_SL: + case ASI_FL8_S: + case ASI_FL8_SL: + case ASI_FL16_S: + case ASI_FL16_SL: if (mem_idx == MMU_USER_IDX) { mem_idx = MMU_USER_SECONDARY_IDX; } else if (mem_idx == MMU_KERNEL_IDX) { @@ -2065,6 +2081,12 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop) case ASI_PL: /* Primary LE */ case ASI_TWINX_P: case ASI_TWINX_PL: + case ASI_BLK_P: + case ASI_BLK_PL: + case ASI_FL8_P: + case ASI_FL8_PL: + case ASI_FL16_P: + case ASI_FL16_PL: break; } switch (asi) { @@ -2092,6 +2114,34 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop) case ASI_TWINX_SL: type = GET_ASI_DTWINX; break; + case ASI_BLK_AIUP_4V: + case ASI_BLK_AIUP_L_4V: + case ASI_BLK_AIUP: + case ASI_BLK_AIUPL: + case ASI_BLK_AIUS_4V: + case ASI_BLK_AIUS_L_4V: + case ASI_BLK_AIUS: + case ASI_BLK_AIUSL: + case ASI_BLK_S: + case ASI_BLK_SL: + case ASI_BLK_P: + case ASI_BLK_PL: + type = GET_ASI_BLOCK; + break; + case ASI_FL8_S: + case ASI_FL8_SL: + case ASI_FL8_P: + case ASI_FL8_PL: + memop = MO_UB; + type = GET_ASI_SHORT; + break; + case ASI_FL16_S: + case ASI_FL16_SL: + case ASI_FL16_P: + case ASI_FL16_PL: + memop = MO_TEUW; + type = GET_ASI_SHORT; + break; } /* The little-endian asis all have bit 3 set. */ if (asi & 8) { @@ -2294,6 +2344,34 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, } break; + case GET_ASI_BLOCK: + /* Valid for lddfa on aligned registers only. */ + if (size == 8 && (rd & 7) == 0) { + int i; + + gen_check_align(addr, 0x3f); + for (i = 0; ; ++i) { + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, + da.mem_idx, da.memop); + if (i == 7) { + break; + } + tcg_gen_addi_tl(addr, addr, 8); + } + } else { + gen_exception(dc, TT_ILL_INSN); + } + break; + + case GET_ASI_SHORT: + /* Valid for lddfa only. */ + if (size == 8) { + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop); + } else { + gen_exception(dc, TT_ILL_INSN); + } + break; + default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); @@ -2339,6 +2417,34 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, } break; + case GET_ASI_BLOCK: + /* Valid for stdfa on aligned registers only. */ + if (size == 8 && (rd & 7) == 0) { + int i; + + gen_check_align(addr, 0x3f); + for (i = 0; ; ++i) { + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, + da.mem_idx, da.memop); + if (i == 7) { + break; + } + tcg_gen_addi_tl(addr, addr, 8); + } + } else { + gen_exception(dc, TT_ILL_INSN); + } + break; + + case GET_ASI_SHORT: + /* Valid for stdfa only. */ + if (size == 8) { + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop); + } else { + gen_exception(dc, TT_ILL_INSN); + } + break; + default: { TCGv_i32 r_asi = tcg_const_i32(da.asi);