From patchwork Thu Feb 11 22:06:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Gabriel L. Somlo" X-Patchwork-Id: 582060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2B03A140BC4 for ; Fri, 12 Feb 2016 09:06:51 +1100 (AEDT) Received: from localhost ([::1]:54013 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTzNv-0003B3-VU for incoming@patchwork.ozlabs.org; Thu, 11 Feb 2016 17:06:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36139) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTzNR-0002FY-Uw for qemu-devel@nongnu.org; Thu, 11 Feb 2016 17:06:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aTzNR-0006v2-15 for qemu-devel@nongnu.org; Thu, 11 Feb 2016 17:06:17 -0500 Received: from relay-06.andrew.cmu.edu ([128.2.157.21]:44129 helo=relay.andrew.cmu.edu) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTzNM-0006sZ-6B; Thu, 11 Feb 2016 17:06:12 -0500 Received: from HEDWIG.ini.cmu.edu (HEDWIG.INI.CMU.EDU [128.2.16.51]) by relay.andrew.cmu.edu (8.14.8/8.14.8) with ESMTP id u1BM6636030587; Thu, 11 Feb 2016 17:06:06 -0500 From: "Gabriel L. Somlo" To: qemu-devel@nongnu.org Date: Thu, 11 Feb 2016 17:06:03 -0500 Message-Id: <1455228365-13666-4-git-send-email-somlo@cmu.edu> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1455228365-13666-1-git-send-email-somlo@cmu.edu> References: <1455228365-13666-1-git-send-email-somlo@cmu.edu> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.74 on 128.2.157.21 X-MIME-Autoconverted: from 8bit to quoted-printable by relay.andrew.cmu.edu id u1BM6636030587 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 128.2.157.21 Cc: peter.maydell@linaro.org, ehabkost@redhat.com, mst@redhat.com, matt@codeblueprint.co.uk, stefanha@gmail.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, luto@amacapital.net, qemu-arm@nongnu.org, kraxel@redhat.com, pbonzini@redhat.com, imammedo@redhat.com, lersek@redhat.com, rth@twiddle.net Subject: [Qemu-devel] [PATCH v8 3/5] acpi: pc: add fw_cfg device node to dsdt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a fw_cfg device node to the ACPI DSDT. While the guest-side firmware can't utilize this information (since it has to access the hard-coded fw_cfg device to extract ACPI tables to begin with), having fw_cfg listed in ACPI will help the guest kernel keep a more accurate inventory of in-use IO port regions. Signed-off-by: Gabriel Somlo Reviewed-by: Laszlo Ersek Reviewed-by: Marc Marí --- hw/i386/acpi-build.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4554eb8..4762fd2 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2190,6 +2190,35 @@ build_dsdt(GArray *table_data, GArray *linker, aml_append(scope, aml_name_decl("_S5", pkg)); aml_append(dsdt, scope); + /* create fw_cfg node, unconditionally */ + { + /* when using port i/o, the 8-bit data register *always* overlaps + * with half of the 16-bit control register. Hence, the total size + * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the + * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ + uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), + "dma_enabled", NULL) ? + ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : + FW_CFG_CTL_SIZE; + + scope = aml_scope("\\_SB"); + dev = aml_device("FWCF"); + + aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); + + /* device present, functioning, decoding, not shown in UI */ + aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); + + crs = aml_resource_template(); + aml_append(crs, + aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) + ); + aml_append(dev, aml_name_decl("_CRS", crs)); + + aml_append(scope, dev); + aml_append(dsdt, scope); + } + if (misc->applesmc_io_base) { scope = aml_scope("\\_SB.PCI0.ISA"); dev = aml_device("SMC");