| Message ID | 1454690704-16233-5-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 05.02.2016 19:45, Peter Maydell wrote: > Implement trapping of the "debug ROM" registers, which are controlled > by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> > --- > target-arm/helper.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 18e85fd..8c2adbc 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -402,6 +402,24 @@ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, > return CP_ACCESS_OK; > } > > +/* Check for traps to "debug ROM" registers, which are controlled > + * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. > + */ > +static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, > + bool isread) > +{ > + int el = arm_current_el(env); > + > + if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) > + && !arm_is_secure_below_el3(env)) { > + return CP_ACCESS_TRAP_EL2; > + } > + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { > + return CP_ACCESS_TRAP_EL3; > + } > + return CP_ACCESS_OK; > +} > + > static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > { > ARMCPU *cpu = arm_env_get_cpu(env); > @@ -3774,12 +3792,15 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { > * accessor. > */ > { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, > - .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, > + .access = PL0_R, .accessfn = access_tdra, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, > - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, > + .access = PL1_R, .accessfn = access_tdra, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, > - .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, > + .access = PL0_R, .accessfn = access_tdra, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ > { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, > .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
diff --git a/target-arm/helper.c b/target-arm/helper.c index 18e85fd..8c2adbc 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -402,6 +402,24 @@ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +/* Check for traps to "debug ROM" registers, which are controlled + * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. + */ +static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) + && !arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = arm_env_get_cpu(env); @@ -3774,12 +3792,15 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { * accessor. */ { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + .access = PL0_R, .accessfn = access_tdra, + .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + .access = PL1_R, .accessfn = access_tdra, + .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + .access = PL0_R, .accessfn = access_tdra, + .type = ARM_CP_CONST, .resetvalue = 0 }, /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
Implement trapping of the "debug ROM" registers, which are controlled by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-)