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[8/9] target-mips: check CP0 enabled for CACHE instruction also in R6

Message ID 1454518611-26134-9-git-send-email-leon.alrae@imgtec.com
State New
Headers show

Commit Message

Leon Alrae Feb. 3, 2016, 4:56 p.m. UTC 
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index c6e2951..3fb3744 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17179,6 +17179,7 @@  static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
         /* Treat as NOP. */
         break;
     case R6_OPC_CACHE:
+        check_cp0_enabled(ctx);
         /* Treat as NOP. */
         break;
     case R6_OPC_SC: