From patchwork Sun Jan 10 15:24:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Herv=C3=A9_Poussineau?= X-Patchwork-Id: 565465 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 58FF5140134 for ; Mon, 11 Jan 2016 02:28:02 +1100 (AEDT) Received: from localhost ([::1]:47255 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aIHuR-00078K-1C for incoming@patchwork.ozlabs.org; Sun, 10 Jan 2016 10:27:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48690) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aIHri-0001ku-Df for qemu-devel@nongnu.org; Sun, 10 Jan 2016 10:25:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aIHrf-0006Te-BD for qemu-devel@nongnu.org; Sun, 10 Jan 2016 10:25:10 -0500 Received: from smtp2-g21.free.fr ([212.27.42.2]:51772) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aIHrf-0006Sr-5V for qemu-devel@nongnu.org; Sun, 10 Jan 2016 10:25:07 -0500 Received: from localhost.localdomain (unknown [82.227.227.196]) by smtp2-g21.free.fr (Postfix) with ESMTP id BF8274B01E8; Sun, 10 Jan 2016 16:23:56 +0100 (CET) From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= To: qemu-devel@nongnu.org Date: Sun, 10 Jan 2016 16:24:43 +0100 Message-Id: <1452439498-21098-5-git-send-email-hpoussin@reactos.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1452439498-21098-1-git-send-email-hpoussin@reactos.org> References: <1452439498-21098-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 212.27.42.2 Cc: Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH v2 04/19] i8257: rename struct dma_regs to I8257Regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Hervé Poussineau --- hw/dma/i8257.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index f4fcf39..e0713a5 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -37,7 +37,7 @@ #define ldebug(...) #endif -struct dma_regs { +typedef struct I8257Regs { int now[2]; uint16_t base[2]; uint8_t mode; @@ -47,7 +47,7 @@ struct dma_regs { uint8_t eop; DMA_transfer_handler transfer_handler; void *opaque; -}; +} I8257Regs; #define ADDR 0 #define COUNT 1 @@ -58,7 +58,7 @@ typedef struct I8257State { uint8_t mask; uint8_t flip_flop; int dshift; - struct dma_regs regs[4]; + I8257Regs regs[4]; MemoryRegion channel_io; MemoryRegion cont_io; } I8257State; @@ -138,7 +138,7 @@ static uint32_t read_pageh (void *opaque, uint32_t nport) static inline void init_chan(I8257State *d, int ichan) { - struct dma_regs *r; + I8257Regs *r; r = d->regs + ichan; r->now[ADDR] = r->base[ADDR] << d->dshift; @@ -158,7 +158,7 @@ static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) { I8257State *d = opaque; int ichan, nreg, iport, ff, val, dir; - struct dma_regs *r; + I8257Regs *r; iport = (nport >> d->dshift) & 0x0f; ichan = iport >> 1; @@ -181,7 +181,7 @@ static void write_chan(void *opaque, hwaddr nport, uint64_t data, { I8257State *d = opaque; int iport, ichan, nreg; - struct dma_regs *r; + I8257Regs *r; iport = (nport >> d->dshift) & 0x0f; ichan = iport >> 1; @@ -337,7 +337,7 @@ void DMA_release_DREQ (int nchan) static void channel_run (int ncont, int ichan) { int n; - struct dma_regs *r = &dma_controllers[ncont].regs[ichan]; + I8257Regs *r = &dma_controllers[ncont].regs[ichan]; #ifdef DEBUG_DMA int dir, opmode; @@ -408,7 +408,7 @@ void DMA_register_channel (int nchan, DMA_transfer_handler transfer_handler, void *opaque) { - struct dma_regs *r; + I8257Regs *r; int ichan, ncont; ncont = nchan > 3; @@ -421,7 +421,7 @@ void DMA_register_channel (int nchan, int DMA_read_memory (int nchan, void *buf, int pos, int len) { - struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; + I8257Regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; if (r->mode & 0x20) { @@ -443,7 +443,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len) int DMA_write_memory (int nchan, void *buf, int pos, int len) { - struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; + I8257Regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; if (r->mode & 0x20) { @@ -552,18 +552,18 @@ static void dma_init2(I8257State *d, int base, int dshift, } } -static const VMStateDescription vmstate_dma_regs = { +static const VMStateDescription vmstate_i8257_regs = { .name = "dma_regs", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_INT32_ARRAY(now, struct dma_regs, 2), - VMSTATE_UINT16_ARRAY(base, struct dma_regs, 2), - VMSTATE_UINT8(mode, struct dma_regs), - VMSTATE_UINT8(page, struct dma_regs), - VMSTATE_UINT8(pageh, struct dma_regs), - VMSTATE_UINT8(dack, struct dma_regs), - VMSTATE_UINT8(eop, struct dma_regs), + VMSTATE_INT32_ARRAY(now, I8257Regs, 2), + VMSTATE_UINT16_ARRAY(base, I8257Regs, 2), + VMSTATE_UINT8(mode, I8257Regs), + VMSTATE_UINT8(page, I8257Regs), + VMSTATE_UINT8(pageh, I8257Regs), + VMSTATE_UINT8(dack, I8257Regs), + VMSTATE_UINT8(eop, I8257Regs), VMSTATE_END_OF_LIST() } }; @@ -585,8 +585,8 @@ static const VMStateDescription vmstate_dma = { VMSTATE_UINT8(mask, I8257State), VMSTATE_UINT8(flip_flop, I8257State), VMSTATE_INT32(dshift, I8257State), - VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_dma_regs, - struct dma_regs), + VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs, + I8257Regs), VMSTATE_END_OF_LIST() } };