From patchwork Thu Dec 17 20:56:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 558622 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BBF1E1401CD for ; Fri, 18 Dec 2015 07:59:21 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=ego3g8OT; dkim-atps=neutral Received: from localhost ([::1]:57117 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9fdv-0000MN-Eu for incoming@patchwork.ozlabs.org; Thu, 17 Dec 2015 15:59:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49053) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9fbj-0004kj-8F for qemu-devel@nongnu.org; Thu, 17 Dec 2015 15:57:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a9fbf-00055U-5S for qemu-devel@nongnu.org; Thu, 17 Dec 2015 15:57:03 -0500 Received: from mail-oi0-x22b.google.com ([2607:f8b0:4003:c06::22b]:36155) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9fbf-00055P-19 for qemu-devel@nongnu.org; Thu, 17 Dec 2015 15:56:59 -0500 Received: by mail-oi0-x22b.google.com with SMTP id o62so44742925oif.3 for ; Thu, 17 Dec 2015 12:56:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=DXIU5yI5wdOAsujSW6LwYuMRvYaCZAWj/Mk5Cc0Hw7Q=; b=ego3g8OTjwceWNSkrgmb6xRZs5B78jCHAIuhvjOrufcgKT4r9rBEKcVLBZ0mtQmpPl KBvDRokZFUB85bTHHGXLRqeATZpF+Nfmzqv3jDqwHNhBVqb2pK/CxfhE63BwnedO7jZs deEJ2Trnect6Gzgi07E3eO0qrUYoV0qpPF8OBa7RNjmvZ7HoNP8851TbOKHd1A/2Ehxh y9Dmi2wwRqUt7df4T8O3e4PSuAisAFQpHuD7ERYqiq/3ypakh5yMr0B4M4lB+YV3PRjx UB6fW3ChwIgIat+q/2paDITEEqB+S+bWl5v/pSwXTzaKma2sSoALVRgL/NRybCh3JOAt 4kPw== X-Received: by 10.202.239.138 with SMTP id n132mr38642019oih.88.1450385818587; Thu, 17 Dec 2015 12:56:58 -0800 (PST) Received: from bigtime.twiddle.net (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id v3sm3058106oeq.14.2015.12.17.12.56.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Dec 2015 12:56:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 17 Dec 2015 12:56:56 -0800 Message-Id: <1450385816-2183-1-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1450385695-1940-1-git-send-email-rth@twiddle.net> References: <1450385695-1940-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4003:c06::22b Cc: mark.cave-ayland@ilande.co.uk, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 10/25] target-sparc: Add UA2011 defines to asi.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-By: Artyom Tarasenko --- target-sparc/asi.h | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/target-sparc/asi.h b/target-sparc/asi.h index aace6f3..c9a1849 100644 --- a/target-sparc/asi.h +++ b/target-sparc/asi.h @@ -144,24 +144,36 @@ * ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-T4 * and later ASIs. */ +#define ASI_REAL 0x14 /* Real address, cachable */ #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */ +#define ASI_REAL_IO 0x15 /* Real address, non-cachable */ #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ #define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */ #define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */ +#define ASI_REAL_L 0x1c /* Real address, cachable, LE */ #define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/ +#define ASI_REAL_IO_L 0x1d /* Real address, non-cachable, LE */ #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ #define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/ #define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */ #define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */ #define ASI_MMU 0x21 /* (4V) MMU Context Registers */ +#define ASI_TWINX_AIUP 0x22 /* twin load, primary user */ +#define ASI_TWINX_AIUS 0x23 /* twin load, secondary user */ #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load, * secondary, user */ #define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */ #define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */ +#define ASI_TWINX_REAL 0x26 /* twin load, real, cachable */ #define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */ +#define ASI_TWINX_N 0x27 /* twin load, nucleus */ +#define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */ +#define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */ #define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */ +#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cachable, LE */ #define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */ +#define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */ #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */ #define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */ #define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */ @@ -267,12 +279,14 @@ #define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/ #define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */ #define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */ +#define ASI_TWINX_P 0xe2 /* twin load, primary implicit */ #define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load, - * primary, implicit - */ + * primary, implicit */ +#define ASI_TWINX_S 0xe3 /* twin load, secondary implicit */ #define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load, - * secondary, implicit - */ + * secondary, implicit */ +#define ASI_TWINX_PL 0xea /* twin load, primary implicit, LE */ +#define ASI_TWINX_SL 0xeb /* twin load, secondary implicit, LE */ #define ASI_BLK_P 0xf0 /* Primary, blk ld/st */ #define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */ #define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load,