From patchwork Thu Dec 17 17:46:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 558528 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 79F121402CD for ; Fri, 18 Dec 2015 05:06:44 +1100 (AEDT) Received: from localhost ([::1]:55636 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9cws-0002a5-2y for incoming@patchwork.ozlabs.org; Thu, 17 Dec 2015 13:06:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51272) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9ceN-0001bM-Gi for qemu-devel@nongnu.org; Thu, 17 Dec 2015 12:47:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a9ceL-0006w3-Hq for qemu-devel@nongnu.org; Thu, 17 Dec 2015 12:47:35 -0500 Received: from mx1.redhat.com ([209.132.183.28]:44024) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9ceL-0006vv-9g for qemu-devel@nongnu.org; Thu, 17 Dec 2015 12:47:33 -0500 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) by mx1.redhat.com (Postfix) with ESMTPS id E39328F01E for ; Thu, 17 Dec 2015 17:47:32 +0000 (UTC) Received: from donizetti.redhat.com (ovpn-112-23.ams2.redhat.com [10.36.112.23]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id tBHHkfcS014618 for ; Thu, 17 Dec 2015 12:47:32 -0500 From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Thu, 17 Dec 2015 18:46:22 +0100 Message-Id: <1450374401-31352-27-git-send-email-pbonzini@redhat.com> In-Reply-To: <1450374401-31352-1-git-send-email-pbonzini@redhat.com> References: <1450374401-31352-1-git-send-email-pbonzini@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 26/45] ppc: cleanup logging X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Avoid "naked" qemu_log, bring documentation for DEBUG #defines up to date. Reviewed-by: David Gibson Signed-off-by: Paolo Bonzini --- target-ppc/excp_helper.c | 1 + target-ppc/mmu-hash32.c | 12 ++---------- target-ppc/mmu-hash64.c | 9 +-------- target-ppc/mmu_helper.c | 15 +++++++-------- target-ppc/timebase_helper.c | 10 ++++++---- target-ppc/translate.c | 22 +++++++++------------- 6 files changed, 26 insertions(+), 43 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 102d789..dbc070c 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -23,6 +23,7 @@ #include "helper_regs.h" //#define DEBUG_OP +//#define DEBUG_SOFTWARE_TLB //#define DEBUG_EXCEPTIONS #ifdef DEBUG_EXCEPTIONS diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index dfee358..a00ae3c 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -24,17 +24,10 @@ #include "kvm_ppc.h" #include "mmu-hash32.h" -//#define DEBUG_MMU //#define DEBUG_BAT -#ifdef DEBUG_MMU -# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) -#else -# define LOG_MMU_STATE(cpu) do { } while (0) -#endif - #ifdef DEBUG_BATS -# define LOG_BATS(...) qemu_log(__VA_ARGS__) +# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__) #else # define LOG_BATS(...) do { } while (0) #endif @@ -281,9 +274,8 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, } return 1; default: - qemu_log("ERROR: instruction should not need " + cpu_abort(cs, "ERROR: instruction should not need " "address translation\n"); - abort(); } if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) { *raddr = eaddr; diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 7df6ede..34e20fa 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -23,17 +23,10 @@ #include "kvm_ppc.h" #include "mmu-hash64.h" -//#define DEBUG_MMU //#define DEBUG_SLB -#ifdef DEBUG_MMU -# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) -#else -# define LOG_MMU_STATE(cpu) do { } while (0) -#endif - #ifdef DEBUG_SLB -# define LOG_SLB(...) qemu_log(__VA_ARGS__) +# define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__) #else # define LOG_SLB(...) do { } while (0) #endif diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 30298d8..5217691 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -28,23 +28,22 @@ //#define DEBUG_BATS //#define DEBUG_SOFTWARE_TLB //#define DUMP_PAGE_TABLES -//#define DEBUG_SOFTWARE_TLB //#define FLUSH_ALL_TLBS #ifdef DEBUG_MMU -# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) +# define LOG_MMU_STATE(cpu) log_cpu_state_mask(CPU_LOG_MMU, (cpu), 0) #else # define LOG_MMU_STATE(cpu) do { } while (0) #endif #ifdef DEBUG_SOFTWARE_TLB -# define LOG_SWTLB(...) qemu_log(__VA_ARGS__) +# define LOG_SWTLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__) #else # define LOG_SWTLB(...) do { } while (0) #endif #ifdef DEBUG_BATS -# define LOG_BATS(...) qemu_log(__VA_ARGS__) +# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__) #else # define LOG_BATS(...) do { } while (0) #endif @@ -162,7 +161,7 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, if (ctx->raddr != (hwaddr)-1ULL) { /* all matches should have equal RPN, WIMG & PP */ if ((ctx->raddr & mmask) != (pte1 & mmask)) { - qemu_log("Bad RPN/WIMG/PP\n"); + qemu_log_mask(CPU_LOG_MMU, "Bad RPN/WIMG/PP\n"); return -3; } } @@ -508,7 +507,7 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, /* Software TLB search */ ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); #if defined(DUMP_PAGE_TABLES) - if (qemu_log_enabled()) { + if (qemu_log_mask(CPU_LOG_MMU)) { hwaddr curaddr; uint32_t a0, a1, a2, a3; @@ -575,8 +574,8 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, /* eciwx or ecowx */ return -4; default: - qemu_log("ERROR: instruction should not need " - "address translation\n"); + qemu_log_mask(CPU_LOG_MMU, "ERROR: instruction should not need " + "address translation\n"); return -4; } if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { diff --git a/target-ppc/timebase_helper.c b/target-ppc/timebase_helper.c index 865dcbe..cafa283 100644 --- a/target-ppc/timebase_helper.c +++ b/target-ppc/timebase_helper.c @@ -130,13 +130,14 @@ target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn) uint32_t val = 0; if (unlikely(env->dcr_env == NULL)) { - qemu_log("No DCR environment\n"); + qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n"); helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); } else if (unlikely(ppc_dcr_read(env->dcr_env, (uint32_t)dcrn, &val) != 0)) { - qemu_log("DCR read error %d %03x\n", (uint32_t)dcrn, (uint32_t)dcrn); + qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n", + (uint32_t)dcrn, (uint32_t)dcrn); helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); } @@ -146,13 +147,14 @@ target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn) void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val) { if (unlikely(env->dcr_env == NULL)) { - qemu_log("No DCR environment\n"); + qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n"); helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); } else if (unlikely(ppc_dcr_write(env->dcr_env, (uint32_t)dcrn, (uint32_t)val) != 0)) { - qemu_log("DCR write error %d %03x\n", (uint32_t)dcrn, (uint32_t)dcrn); + qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n", + (uint32_t)dcrn, (uint32_t)dcrn); helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); } diff --git a/target-ppc/translate.c b/target-ppc/translate.c index cdf46dd..4be7eaa 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11530,12 +11530,10 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) } /* Is opcode *REALLY* valid ? */ if (unlikely(handler->handler == &gen_invalid)) { - if (qemu_log_enabled()) { - qemu_log("invalid/unsupported opcode: " - "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", - opc1(ctx.opcode), opc2(ctx.opcode), - opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); - } + qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " + "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", + opc1(ctx.opcode), opc2(ctx.opcode), + opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); } else { uint32_t inval; @@ -11546,13 +11544,11 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) } if (unlikely((ctx.opcode & inval) != 0)) { - if (qemu_log_enabled()) { - qemu_log("invalid bits: %08x for opcode: " - "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", - ctx.opcode & inval, opc1(ctx.opcode), - opc2(ctx.opcode), opc3(ctx.opcode), - ctx.opcode, ctx.nip - 4); - } + qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " + "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", + ctx.opcode & inval, opc1(ctx.opcode), + opc2(ctx.opcode), opc3(ctx.opcode), + ctx.opcode, ctx.nip - 4); gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); break; }