From patchwork Thu Dec 10 06:15:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharata B Rao X-Patchwork-Id: 554998 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2BCD0140E6E for ; Thu, 10 Dec 2015 17:19:23 +1100 (AEDT) Received: from localhost ([::1]:39587 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a6uZU-0006qD-Rr for incoming@patchwork.ozlabs.org; Thu, 10 Dec 2015 01:19:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44875) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a6uXO-0002s8-AD for qemu-devel@nongnu.org; Thu, 10 Dec 2015 01:17:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a6uXL-00038j-07 for qemu-devel@nongnu.org; Thu, 10 Dec 2015 01:17:10 -0500 Received: from e23smtp03.au.ibm.com ([202.81.31.145]:34259) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a6uXK-00038Z-D2 for qemu-devel@nongnu.org; Thu, 10 Dec 2015 01:17:06 -0500 Received: from localhost by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 10 Dec 2015 16:17:04 +1000 Received: from d23dlp03.au.ibm.com (202.81.31.214) by e23smtp03.au.ibm.com (202.81.31.209) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Thu, 10 Dec 2015 16:17:03 +1000 X-IBM-Helo: d23dlp03.au.ibm.com X-IBM-MailFrom: bharata@linux.vnet.ibm.com X-IBM-RcptTo: qemu-devel@nongnu.org Received: from d23relay07.au.ibm.com (d23relay07.au.ibm.com [9.190.26.37]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id F353F3578052 for ; Thu, 10 Dec 2015 17:17:02 +1100 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id tBA6GuIB32243962 for ; Thu, 10 Dec 2015 17:17:04 +1100 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id tBA6GT1K030613 for ; Thu, 10 Dec 2015 17:16:30 +1100 Received: from bharata.in.ibm.com ([9.124.35.218]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id tBA6G8Bg028490; Thu, 10 Dec 2015 17:16:27 +1100 From: Bharata B Rao To: qemu-devel@nongnu.org Date: Thu, 10 Dec 2015 11:45:43 +0530 Message-Id: <1449728144-6223-9-git-send-email-bharata@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1449728144-6223-1-git-send-email-bharata@linux.vnet.ibm.com> References: <1449728144-6223-1-git-send-email-bharata@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15121006-0009-0000-0000-00000281F8F4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 202.81.31.145 Cc: peter.maydell@linaro.org, ehabkost@redhat.com, Bharata B Rao , agraf@suse.de, borntraeger@de.ibm.com, imammedo@redhat.com, pbonzini@redhat.com, afaerber@suse.de, david@gibson.dropbear.id.au Subject: [Qemu-devel] [RFC PATCH v0 8/9] target-i386: Set apic_id during CPU initfn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Move back the setting of apic_id to instance_init routine (x86_cpu_initfn) This is needed to initialize X86 CPUs using generic cpu-package device. TODO: I am not fully aware of the general direction in which apic_id changes in X86 have evolved and hence not sure if this is indeed aligned with the X86 way of doing things. This is just to help the PoC implementation that I have in this patchset to convert PC CPUs initialization into cpu-package device based initialization. Signed-off-by: Bharata B Rao --- hw/i386/pc.c | 33 --------------------------------- target-i386/cpu.c | 37 +++++++++++++++++++++++++++++++++++-- target-i386/cpu.h | 1 + 3 files changed, 36 insertions(+), 35 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index ffcd645..80a4d98 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -670,39 +670,6 @@ bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) return false; } -/* Enables contiguous-apic-ID mode, for compatibility */ -static bool compat_apic_id_mode; - -void enable_compat_apic_id_mode(void) -{ - compat_apic_id_mode = true; -} - -/* Calculates initial APIC ID for a specific CPU index - * - * Currently we need to be able to calculate the APIC ID from the CPU index - * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have - * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of - * all CPUs up to max_cpus. - */ -static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) -{ - uint32_t correct_id; - static bool warned; - - correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); - if (compat_apic_id_mode) { - if (cpu_index != correct_id && !warned && !qtest_enabled()) { - error_report("APIC IDs set in compatibility mode, " - "CPU topology won't match the configuration"); - warned = true; - } - return cpu_index; - } else { - return correct_id; - } -} - /* Calculates the limit to CPU APIC ID values * * This function returns the limit for the APIC ID value, so that all diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 11e5e39..c97a646 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -25,6 +25,7 @@ #include "sysemu/kvm.h" #include "sysemu/cpus.h" #include "kvm_i386.h" +#include "hw/i386/topology.h" #include "qemu/error-report.h" #include "qemu/option.h" @@ -3028,6 +3029,39 @@ static void x86_cpu_register_feature_bit_props(X86CPU *cpu, g_strfreev(names); } +/* Enables contiguous-apic-ID mode, for compatibility */ +static bool compat_apic_id_mode; + +void enable_compat_apic_id_mode(void) +{ + compat_apic_id_mode = true; +} + +/* Calculates initial APIC ID for a specific CPU index + * + * Currently we need to be able to calculate the APIC ID from the CPU index + * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have + * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of + * all CPUs up to max_cpus. + */ +uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) +{ + uint32_t correct_id; + static bool warned; + + correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); + if (compat_apic_id_mode) { + if (cpu_index != correct_id && !warned) { + error_report("APIC IDs set in compatibility mode, " + "CPU topology won't match the configuration"); + warned = true; + } + return cpu_index; + } else { + return correct_id; + } +} + static void x86_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); @@ -3071,8 +3105,7 @@ static void x86_cpu_initfn(Object *obj) cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY; #ifndef CONFIG_USER_ONLY - /* Any code creating new X86CPU objects have to set apic-id explicitly */ - cpu->apic_id = -1; + cpu->apic_id = x86_cpu_apic_id_from_index(cs->cpu_index); #endif for (w = 0; w < FEATURE_WORDS; w++) { diff --git a/target-i386/cpu.h b/target-i386/cpu.h index fc4a605..a5368cf 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1333,6 +1333,7 @@ void x86_cpu_change_kvm_default(const char *prop, const char *value); /* Return name of 32-bit register, from a R_* constant */ const char *get_register_name_32(unsigned int reg); +uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index); void enable_compat_apic_id_mode(void); #define APIC_DEFAULT_ADDRESS 0xfee00000