From patchwork Thu Dec 10 06:15:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharata B Rao X-Patchwork-Id: 555000 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 840FC140E6E for ; Thu, 10 Dec 2015 17:19:37 +1100 (AEDT) Received: from localhost ([::1]:39589 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a6uZj-0007EL-9x for incoming@patchwork.ozlabs.org; Thu, 10 Dec 2015 01:19:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44803) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a6uXF-0002aD-1c for qemu-devel@nongnu.org; Thu, 10 Dec 2015 01:17:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a6uXB-00036t-MJ for qemu-devel@nongnu.org; Thu, 10 Dec 2015 01:17:00 -0500 Received: from e23smtp06.au.ibm.com ([202.81.31.148]:52735) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a6uXA-00036m-Sh for qemu-devel@nongnu.org; Thu, 10 Dec 2015 01:16:57 -0500 Received: from localhost by e23smtp06.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 10 Dec 2015 16:16:51 +1000 X-IBM-Helo: d23dlp01.au.ibm.com X-IBM-MailFrom: bharata@linux.vnet.ibm.com X-IBM-RcptTo: qemu-devel@nongnu.org Received: from d23relay07.au.ibm.com (d23relay07.au.ibm.com [9.190.26.37]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id C28C82CE805A for ; Thu, 10 Dec 2015 17:16:50 +1100 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id tBA6GiFX31654044 for ; Thu, 10 Dec 2015 17:16:52 +1100 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id tBA6GIem029784 for ; Thu, 10 Dec 2015 17:16:18 +1100 Received: from bharata.in.ibm.com ([9.124.35.218]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id tBA6G8Bb028490; Thu, 10 Dec 2015 17:16:16 +1100 From: Bharata B Rao To: qemu-devel@nongnu.org Date: Thu, 10 Dec 2015 11:45:38 +0530 Message-Id: <1449728144-6223-4-git-send-email-bharata@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1449728144-6223-1-git-send-email-bharata@linux.vnet.ibm.com> References: <1449728144-6223-1-git-send-email-bharata@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15121006-0021-0000-0000-0000024DAB6E X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 202.81.31.148 Cc: peter.maydell@linaro.org, ehabkost@redhat.com, Bharata B Rao , agraf@suse.de, borntraeger@de.ibm.com, imammedo@redhat.com, pbonzini@redhat.com, afaerber@suse.de, david@gibson.dropbear.id.au Subject: [Qemu-devel] [RFC PATCH v0 3/9] cpu: Don't realize CPU from cpu_generic_init() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Don't do CPU realization from cpu_generic_init(). With this cpu_generic_init() can be used from instance_init to just create CPU threads and they could be realized separately from realizefn call. Convert the existing callers to do explicit realization. Signed-off-by: Bharata B Rao --- qom/cpu.c | 6 ------ target-arm/helper.c | 16 +++++++++++++++- target-cris/cpu.c | 16 +++++++++++++++- target-lm32/helper.c | 16 +++++++++++++++- target-moxie/cpu.c | 16 +++++++++++++++- target-openrisc/cpu.c | 16 +++++++++++++++- target-ppc/translate_init.c | 16 +++++++++++++++- target-sh4/cpu.c | 16 +++++++++++++++- target-tricore/helper.c | 16 +++++++++++++++- target-unicore32/helper.c | 16 +++++++++++++++- 10 files changed, 135 insertions(+), 15 deletions(-) diff --git a/qom/cpu.c b/qom/cpu.c index fb80d13..e7a17c1 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -63,13 +63,7 @@ CPUState *cpu_generic_init(const char *typename, const char *cpu_model) featurestr = strtok(NULL, ","); cc->parse_features(cpu, featurestr, &err); g_free(str); - if (err != NULL) { - goto out; - } - - object_property_set_bool(OBJECT(cpu), true, "realized", &err); -out: if (err != NULL) { error_report_err(err); object_unref(OBJECT(cpu)); diff --git a/target-arm/helper.c b/target-arm/helper.c index 4ecae61..0d8c94e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4546,7 +4546,21 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPU *cpu_arm_init(const char *cpu_model) { - return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_ARM_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return ARM_CPU(cpu); + } } void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 8eaf5a5..d2c0822 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -89,7 +89,21 @@ static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) CRISCPU *cpu_cris_init(const char *cpu_model) { - return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_CRIS_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return CRIS_CPU(cpu); + } } /* Sort alphabetically by VR. */ diff --git a/target-lm32/helper.c b/target-lm32/helper.c index e26c133..49ac960 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -218,7 +218,21 @@ bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request) LM32CPU *cpu_lm32_init(const char *cpu_model) { - return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_LM32_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return LM32_CPU(cpu); + } } /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 0c60c65..5989fa6 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -152,7 +152,21 @@ static const MoxieCPUInfo moxie_cpus[] = { MoxieCPU *cpu_moxie_init(const char *cpu_model) { - return MOXIE_CPU(cpu_generic_init(TYPE_MOXIE_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_MOXIE_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return MOXIE_CPU(cpu); + } } static void cpu_register(const MoxieCPUInfo *info) diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index cc5e2d1..873eafb 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -222,7 +222,21 @@ static void openrisc_cpu_register_types(void) OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) { - return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return OPENRISC_CPU(cpu); + } } /* Sort alphabetically by type name, except for "any". */ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index e88dc7f..d5ae53e 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9373,7 +9373,21 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name) PowerPCCPU *cpu_ppc_init(const char *cpu_model) { - return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_POWERPC_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return POWERPC_CPU(cpu); + } } /* Sort by PVR, ordering special case "host" last. */ diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index d7e2fbd..e5151a0 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -155,7 +155,21 @@ static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) SuperHCPU *cpu_sh4_init(const char *cpu_model) { - return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_SUPERH_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return SUPERH_CPU(cpu); + } } static void sh7750r_cpu_initfn(Object *obj) diff --git a/target-tricore/helper.c b/target-tricore/helper.c index 1808b28..7dcd176 100644 --- a/target-tricore/helper.c +++ b/target-tricore/helper.c @@ -83,7 +83,21 @@ int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address, TriCoreCPU *cpu_tricore_init(const char *cpu_model) { - return TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_TRICORE_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return TRICORE_CPU(cpu); + } } static void tricore_cpu_list_entry(gpointer data, gpointer user_data) diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index ae63277..e47bb12 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -27,7 +27,21 @@ UniCore32CPU *uc32_cpu_init(const char *cpu_model) { - return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return UNICORE32_CPU(cpu); + } } uint32_t HELPER(clo)(uint32_t x)