From patchwork Fri Dec 4 07:47:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cao jin X-Patchwork-Id: 552598 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AC06E140297 for ; Fri, 4 Dec 2015 18:47:30 +1100 (AEDT) Received: from localhost ([::1]:39208 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a4l5U-0000cr-Jh for incoming@patchwork.ozlabs.org; Fri, 04 Dec 2015 02:47:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a4l4T-0007on-6X for qemu-devel@nongnu.org; Fri, 04 Dec 2015 02:46:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a4l4S-0000PT-0x for qemu-devel@nongnu.org; Fri, 04 Dec 2015 02:46:25 -0500 Received: from [59.151.112.132] (port=65198 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a4l4O-0000CT-Cg; Fri, 04 Dec 2015 02:46:20 -0500 X-IronPort-AV: E=Sophos;i="5.20,346,1444665600"; d="scan'208";a="1191426" Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 04 Dec 2015 15:45:54 +0800 Received: from G08CNEXCHPEKD01.g08.fujitsu.local (unknown [10.167.33.80]) by cn.fujitsu.com (Postfix) with ESMTP id 279D440444C4; Fri, 4 Dec 2015 15:45:50 +0800 (CST) Received: from G08FNSTD140223.g08.fujitsu.local (10.167.226.96) by G08CNEXCHPEKD01.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.181.6; Fri, 4 Dec 2015 15:45:49 +0800 From: Cao jin To: Date: Fri, 4 Dec 2015 15:47:17 +0800 Message-ID: <1449215238-4492-2-git-send-email-caoj.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1449215238-4492-1-git-send-email-caoj.fnst@cn.fujitsu.com> References: <1449215238-4492-1-git-send-email-caoj.fnst@cn.fujitsu.com> MIME-Version: 1.0 X-Originating-IP: [10.167.226.96] X-yoursite-MailScanner-Information: Please contact the ISP for more information X-yoursite-MailScanner-ID: 279D440444C4.A8A86 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: caoj.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Cc: qemu-block@nongnu.org, mst@redhat.com, jasowang@redhat.com, alex.williamson@redhat.com, hare@suse.de, dmitry@daynix.com, pbonzini@redhat.com, jsnow@redhat.com, kraxel@redhat.com Subject: [Qemu-devel] [PATCH for-2.6 1/2] Add param Error** to msi_init() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org msi_init() is a supporting function in PCI device initialization, in order to convert .init() to .realize(), it should be modified first. Bonus: add more comment. Signed-off-by: Cao jin --- hw/pci/msi.c | 17 +++++++++++++---- include/hw/pci/msi.h | 4 ++-- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/hw/pci/msi.c b/hw/pci/msi.c index c1dd531..1f5d9e8 100644 --- a/hw/pci/msi.c +++ b/hw/pci/msi.c @@ -150,15 +150,23 @@ bool msi_enabled(const PCIDevice *dev) PCI_MSI_FLAGS_ENABLE); } -int msi_init(struct PCIDevice *dev, uint8_t offset, - unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask) +/* + * @nr_vectors: Multiple Message Capable field of Message Control register + * @msi64bit: support 64-bit message address or not + * @msi_per_vector_mask: support per-vector masking or not + * + * return: MSI capability offset in config space + */ +int msi_init(struct PCIDevice *dev, uint8_t offset, unsigned int nr_vectors, + bool msi64bit, bool msi_per_vector_mask, Error **errp) { unsigned int vectors_order; - uint16_t flags; + uint16_t flags; /* Message Control register value */ uint8_t cap_size; int config_offset; if (!msi_supported) { + error_setg(errp, "MSI/MSI-X is not supported by interrupt controller"); return -ENOTSUP; } @@ -182,7 +190,7 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, } cap_size = msi_cap_sizeof(flags); - config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size); + config_offset = pci_add_capability2(dev, PCI_CAP_ID_MSI, offset, cap_size, errp); if (config_offset < 0) { return config_offset; } @@ -205,6 +213,7 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit), 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors)); } + return config_offset; } diff --git a/include/hw/pci/msi.h b/include/hw/pci/msi.h index 50e452b..da1dc1a 100644 --- a/include/hw/pci/msi.h +++ b/include/hw/pci/msi.h @@ -34,8 +34,8 @@ extern bool msi_supported; void msi_set_message(PCIDevice *dev, MSIMessage msg); MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector); bool msi_enabled(const PCIDevice *dev); -int msi_init(struct PCIDevice *dev, uint8_t offset, - unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask); +int msi_init(struct PCIDevice *dev, uint8_t offset, unsigned int nr_vectors, + bool msi64bit, bool msi_per_vector_mask, Error **errp); void msi_uninit(struct PCIDevice *dev); void msi_reset(PCIDevice *dev); void msi_notify(PCIDevice *dev, unsigned int vector);