From patchwork Wed Nov 11 02:34:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 542759 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9EBD9141418 for ; Wed, 11 Nov 2015 13:34:39 +1100 (AEDT) Received: from localhost ([::1]:37294 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZwLF7-0001OL-AF for incoming@patchwork.ozlabs.org; Tue, 10 Nov 2015 21:34:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47718) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZwLEg-0000eW-IQ for qemu-devel@nongnu.org; Tue, 10 Nov 2015 21:34:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZwLEe-00030C-4l for qemu-devel@nongnu.org; Tue, 10 Nov 2015 21:34:10 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:51559) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZwLEd-0002zH-Oq; Tue, 10 Nov 2015 21:34:08 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 23EB2141418; Wed, 11 Nov 2015 13:34:05 +1100 (AEDT) From: David Gibson To: peter.maydell@linaro.org Date: Wed, 11 Nov 2015 13:34:33 +1100 Message-Id: <1447209276-20146-2-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1447209276-20146-1-git-send-email-david@gibson.dropbear.id.au> References: <1447209276-20146-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2401:3900:2:1::2 Cc: lvivier@redhat.com, thuth@redhat.com, qemu-devel@nongnu.org, aik@ozlabs.ru, agraf@suse.de, mdroth@linux.vnet.ibm.com, qemu-ppc@nongnu.org, Bharata B Rao , David Gibson Subject: [Qemu-devel] [PULL 1/4] ppc: Add/Re-introduce MMU model definitions needed by PR KVM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Bharata B Rao Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and 2.07) removed the mmu_model definition POWERPC_MMU_2_06a which is needed by PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting of PR KVM guest. Signed-off-by: Bharata B Rao Cc: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/cpu.h | 6 ++++++ target-ppc/mmu_helper.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index b34aed6..31c6fee 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -122,9 +122,15 @@ enum powerpc_mmu_t { /* Architecture 2.06 variant */ POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_AMR | 0x00000003, + /* Architecture 2.06 "degraded" (no 1T segments) */ + POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR + | 0x00000003, /* Architecture 2.07 variant */ POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_AMR | 0x00000004, + /* Architecture 2.07 "degraded" (no 1T segments) */ + POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR + | 0x00000004, #endif /* defined(TARGET_PPC64) */ }; diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index e52d0e5..30298d8 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1295,7 +1295,9 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: dump_slb(f, cpu_fprintf, env); break; #endif @@ -1435,7 +1437,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: return ppc_hash64_get_phys_page_debug(env, addr); #endif @@ -1939,7 +1943,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: #endif /* defined(TARGET_PPC64) */ tlb_flush(CPU(cpu), 1); break; @@ -2013,7 +2019,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate, * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,