| Message ID | 1447201710-10229-9-git-send-email-benh@kernel.crashing.org |
|---|---|
| State | New |
| Headers | show |
On Wed, Nov 11, 2015 at 11:27:21AM +1100, Benjamin Herrenschmidt wrote: > Also use it to clamp the max SMT mode and ensure that the cpu_dt_id > are offset by that value in order to preserve consistency with the > HW implementations. > > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > target-ppc/cpu-qom.h | 1 + > target-ppc/translate_init.c | 8 +++++++- > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h > index 6967a80..fef23fd 100644 > --- a/target-ppc/cpu-qom.h > +++ b/target-ppc/cpu-qom.h > @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass { > uint32_t flags; > int bfd_mach; > uint32_t l1_dcache_size, l1_icache_size; > + uint32_t threads_per_core; > #if defined(TARGET_PPC64) > const struct ppc_segment_page_sizes *sps; > #endif > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index c743eb1..1d402e1 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -8193,6 +8193,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) > POWERPC_FLAG_BUS_CLK; > pcc->l1_dcache_size = 0x8000; > pcc->l1_icache_size = 0x10000; > + pcc->threads_per_core = 2; > } > > static void powerpc_get_compat(Object *obj, Visitor *v, > @@ -8339,6 +8340,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) > pcc->l1_dcache_size = 0x8000; > pcc->l1_icache_size = 0x8000; > pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; > + pcc->threads_per_core = 4; > } > > static void init_proc_POWER8(CPUPPCState *env) > @@ -8419,6 +8421,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > pcc->l1_dcache_size = 0x8000; > pcc->l1_icache_size = 0x8000; > pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; > + pcc->threads_per_core = 8; > } > #endif /* defined (TARGET_PPC64) */ > > @@ -9074,6 +9077,9 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) > #endif > > #if !defined(CONFIG_USER_ONLY) > + if (max_smt > pcc->threads_per_core) { > + max_smt = pcc->threads_per_core; > + } > if (smp_threads > max_smt) { > error_setg(errp, "Cannot support more than %d threads on PPC with %s", > max_smt, kvm_enabled() ? "KVM" : "TCG"); > @@ -9094,7 +9100,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) > } > > #if !defined(CONFIG_USER_ONLY) > - cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt > + cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc->threads_per_core > + (cs->cpu_index % smp_threads); > #endif >
On Mon, 2015-11-16 at 16:16 +1100, David Gibson wrote: > On Wed, Nov 11, 2015 at 11:27:21AM +1100, Benjamin Herrenschmidt > wrote: > > Also use it to clamp the max SMT mode and ensure that the cpu_dt_id > > are offset by that value in order to preserve consistency with the > > HW implementations. > > > > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > Reviewed-by: David Gibson <david@gibson.dropbear.id.au> In fact this is broken ;-) All the CPUs without thread get 0 in the new field which trips at init time since we can create 0 threads :-) It broke for example 32-bit stuff. I've fixed that in github. > > --- > > target-ppc/cpu-qom.h | 1 + > > target-ppc/translate_init.c | 8 +++++++- > > 2 files changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h > > index 6967a80..fef23fd 100644 > > --- a/target-ppc/cpu-qom.h > > +++ b/target-ppc/cpu-qom.h > > @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass { > > uint32_t flags; > > int bfd_mach; > > uint32_t l1_dcache_size, l1_icache_size; > > + uint32_t threads_per_core; > > #if defined(TARGET_PPC64) > > const struct ppc_segment_page_sizes *sps; > > #endif > > diff --git a/target-ppc/translate_init.c b/target- > > ppc/translate_init.c > > index c743eb1..1d402e1 100644 > > --- a/target-ppc/translate_init.c > > +++ b/target-ppc/translate_init.c > > @@ -8193,6 +8193,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void > > *data) > > POWERPC_FLAG_BUS_CLK; > > pcc->l1_dcache_size = 0x8000; > > pcc->l1_icache_size = 0x10000; > > + pcc->threads_per_core = 2; > > } > > > > static void powerpc_get_compat(Object *obj, Visitor *v, > > @@ -8339,6 +8340,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void > > *data) > > pcc->l1_dcache_size = 0x8000; > > pcc->l1_icache_size = 0x8000; > > pcc->interrupts_big_endian = > > ppc_cpu_interrupts_big_endian_lpcr; > > + pcc->threads_per_core = 4; > > } > > > > static void init_proc_POWER8(CPUPPCState *env) > > @@ -8419,6 +8421,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void > > *data) > > pcc->l1_dcache_size = 0x8000; > > pcc->l1_icache_size = 0x8000; > > pcc->interrupts_big_endian = > > ppc_cpu_interrupts_big_endian_lpcr; > > + pcc->threads_per_core = 8; > > } > > #endif /* defined (TARGET_PPC64) */ > > > > @@ -9074,6 +9077,9 @@ static void ppc_cpu_realizefn(DeviceState > > *dev, Error **errp) > > #endif > > > > #if !defined(CONFIG_USER_ONLY) > > + if (max_smt > pcc->threads_per_core) { > > + max_smt = pcc->threads_per_core; > > + } > > if (smp_threads > max_smt) { > > error_setg(errp, "Cannot support more than %d threads on > > PPC with %s", > > max_smt, kvm_enabled() ? "KVM" : "TCG"); > > @@ -9094,7 +9100,7 @@ static void ppc_cpu_realizefn(DeviceState > > *dev, Error **errp) > > } > > > > #if !defined(CONFIG_USER_ONLY) > > - cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt > > + cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc- > > >threads_per_core > > + (cs->cpu_index % smp_threads); > > #endif > > >
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index 6967a80..fef23fd 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass { uint32_t flags; int bfd_mach; uint32_t l1_dcache_size, l1_icache_size; + uint32_t threads_per_core; #if defined(TARGET_PPC64) const struct ppc_segment_page_sizes *sps; #endif diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index c743eb1..1d402e1 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8193,6 +8193,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) POWERPC_FLAG_BUS_CLK; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x10000; + pcc->threads_per_core = 2; } static void powerpc_get_compat(Object *obj, Visitor *v, @@ -8339,6 +8340,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; + pcc->threads_per_core = 4; } static void init_proc_POWER8(CPUPPCState *env) @@ -8419,6 +8421,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; + pcc->threads_per_core = 8; } #endif /* defined (TARGET_PPC64) */ @@ -9074,6 +9077,9 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) #endif #if !defined(CONFIG_USER_ONLY) + if (max_smt > pcc->threads_per_core) { + max_smt = pcc->threads_per_core; + } if (smp_threads > max_smt) { error_setg(errp, "Cannot support more than %d threads on PPC with %s", max_smt, kvm_enabled() ? "KVM" : "TCG"); @@ -9094,7 +9100,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) } #if !defined(CONFIG_USER_ONLY) - cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt + cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc->threads_per_core + (cs->cpu_index % smp_threads); #endif
Also use it to clamp the max SMT mode and ensure that the cpu_dt_id are offset by that value in order to preserve consistency with the HW implementations. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> --- target-ppc/cpu-qom.h | 1 + target-ppc/translate_init.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-)