| Message ID | 1447201710-10229-8-git-send-email-benh@kernel.crashing.org |
|---|---|
| State | New |
| Headers | show |
On Wed, Nov 11, 2015 at 11:27:20AM +1100, Benjamin Herrenschmidt wrote: > We don't give them a KVM reg number yet as no current KVM version > supports HV mode. > > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Looks sane, though I haven't explicitly checked each of the implementations against the architecture. > --- > target-ppc/translate_init.c | 140 +++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 137 insertions(+), 3 deletions(-) > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 30a03ce..c743eb1 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -1104,6 +1104,11 @@ static void gen_spr_amr (CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > KVM_REG_PPC_UAMOR, 0); > + spr_register_hv(env, SPR_AMOR, "AMOR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0); > #endif /* !CONFIG_USER_ONLY */ > } > #endif /* TARGET_PPC64 */ > @@ -7490,6 +7495,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env) > KVM_REG_PPC_DABRX, 0x00000000); > } > > +static void gen_spr_book3s_207_dbg(CPUPPCState *env) > +{ > + spr_register_hv(env, SPR_DAWR, "DAWR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_DAWRX, "DAWRX", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > +} > + > static void gen_spr_970_dbg(CPUPPCState *env) > { > /* Breakpoints */ > @@ -7654,15 +7673,116 @@ static void gen_spr_power5p_lpar(CPUPPCState *env) > spr_register_kvm(env, SPR_LPCR, "LPCR", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > - KVM_REG_PPC_LPCR, 0x00000000); > + KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); > } > > +#if !defined(CONFIG_USER_ONLY) > +static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) > +{ > + TCGv hmer = tcg_temp_new(); > + > + gen_load_spr(hmer, sprn); > + tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); > + gen_store_spr(sprn, hmer); > + spr_store_dump_spr(sprn); > + tcg_temp_free(hmer); > +} > +#endif > + > static void gen_spr_book3s_ids(CPUPPCState *env) > { > + /* FIXME: Will need to deal with thread vs core only SPRs */ > + > /* Processor identification */ > - spr_register(env, SPR_PIR, "PIR", > + spr_register_hv(env, SPR_PIR, "PIR", > SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_pir, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, NULL, > + 0x00000000); > + spr_register_hv(env, SPR_HID0, "HID0", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_TSCR, "TSCR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_HMER, "HMER", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_hmer, > + 0x00000000); > + spr_register_hv(env, SPR_HMEER, "HMEER", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_TFMR, "TFMR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_LPIDR, "LPIDR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_HFSCR, "HFSCR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_MMCRC, "MMCRC", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_MMCRH, "MMCRH", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_HSPRG0, "HSPRG0", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_HSPRG1, "HSPRG1", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_HSRR0, "HSRR0", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_HSRR1, "HSRR1", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_HDAR, "HDAR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_HDSISR, "HDSISR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_RMOR, "RMOR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_HRMOR, "HRMOR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > 0x00000000); > } > > @@ -7868,6 +7988,17 @@ static void gen_spr_power8_fscr(CPUPPCState *env) > KVM_REG_PPC_FSCR, initval); > } > > +static void gen_spr_power8_rpr(CPUPPCState *env) > +{ > +#if !defined(CONFIG_USER_ONLY) > + spr_register_hv(env, SPR_RPR, "RPR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000103070F1F3F); > +#endif > +} > + > static void init_proc_book3s_64(CPUPPCState *env, int version) > { > gen_spr_ne_601(env); > @@ -7919,9 +8050,12 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) > gen_spr_power8_pmu_user(env); > gen_spr_power8_tm(env); > gen_spr_vtb(env); > + gen_spr_power8_rpr(env); > } > if (version < BOOK3S_CPU_POWER8) { > gen_spr_book3s_dbg(env); > + } else { > + gen_spr_book3s_207_dbg(env); > } > #if !defined(CONFIG_USER_ONLY) > switch (version) {
On Thu, 2015-11-19 at 17:11 +1100, David Gibson wrote: > On Wed, Nov 11, 2015 at 11:27:20AM +1100, Benjamin Herrenschmidt > wrote: > > We don't give them a KVM reg number yet as no current KVM version > > supports HV mode. > > > > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > Looks sane, though I haven't explicitly checked each of the > implementations against the architecture. Almost all of those are just "placeholders". IE, we just read and write whatever is passed into the SPR array. What might be interesting is to what extend we actually use the values later on, which happens by bits and pieces in separate patches, or in many cases, not at all. I think it might be worth adding to the SPR array a bitmask of the implemented bits though, so that we force the unimplemented ones to 0 rather than storing them, and possibly warn on attempts to write 1 to an unimplemented one. Something to put on the TODO list... Cheers, Ben. > > --- > > target-ppc/translate_init.c | 140 > > +++++++++++++++++++++++++++++++++++++++++++- > > 1 file changed, 137 insertions(+), 3 deletions(-) > > > > diff --git a/target-ppc/translate_init.c b/target- > > ppc/translate_init.c > > index 30a03ce..c743eb1 100644 > > --- a/target-ppc/translate_init.c > > +++ b/target-ppc/translate_init.c > > @@ -1104,6 +1104,11 @@ static void gen_spr_amr (CPUPPCState *env) > > SPR_NOACCESS, SPR_NOACCESS, > > &spr_read_generic, &spr_write_generic, > > KVM_REG_PPC_UAMOR, 0); > > + spr_register_hv(env, SPR_AMOR, "AMOR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0); > > #endif /* !CONFIG_USER_ONLY */ > > } > > #endif /* TARGET_PPC64 */ > > @@ -7490,6 +7495,20 @@ static void gen_spr_book3s_dbg(CPUPPCState > > *env) > > KVM_REG_PPC_DABRX, 0x00000000); > > } > > > > +static void gen_spr_book3s_207_dbg(CPUPPCState *env) > > +{ > > + spr_register_hv(env, SPR_DAWR, "DAWR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_DAWRX, "DAWRX", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > +} > > + > > static void gen_spr_970_dbg(CPUPPCState *env) > > { > > /* Breakpoints */ > > @@ -7654,15 +7673,116 @@ static void > > gen_spr_power5p_lpar(CPUPPCState *env) > > spr_register_kvm(env, SPR_LPCR, "LPCR", > > SPR_NOACCESS, SPR_NOACCESS, > > &spr_read_generic, &spr_write_generic, > > - KVM_REG_PPC_LPCR, 0x00000000); > > + KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); > > } > > > > +#if !defined(CONFIG_USER_ONLY) > > +static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) > > +{ > > + TCGv hmer = tcg_temp_new(); > > + > > + gen_load_spr(hmer, sprn); > > + tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); > > + gen_store_spr(sprn, hmer); > > + spr_store_dump_spr(sprn); > > + tcg_temp_free(hmer); > > +} > > +#endif > > + > > static void gen_spr_book3s_ids(CPUPPCState *env) > > { > > + /* FIXME: Will need to deal with thread vs core only SPRs */ > > + > > /* Processor identification */ > > - spr_register(env, SPR_PIR, "PIR", > > + spr_register_hv(env, SPR_PIR, "PIR", > > SPR_NOACCESS, SPR_NOACCESS, > > - &spr_read_generic, &spr_write_pir, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, NULL, > > + 0x00000000); > > + spr_register_hv(env, SPR_HID0, "HID0", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_TSCR, "TSCR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_HMER, "HMER", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_hmer, > > + 0x00000000); > > + spr_register_hv(env, SPR_HMEER, "HMEER", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_TFMR, "TFMR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_LPIDR, "LPIDR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_HFSCR, "HFSCR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_MMCRC, "MMCRC", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_MMCRH, "MMCRH", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_HSPRG0, "HSPRG0", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_HSPRG1, "HSPRG1", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_HSRR0, "HSRR0", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_HSRR1, "HSRR1", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_HDAR, "HDAR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_HDSISR, "HDSISR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_RMOR, "RMOR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000000); > > + spr_register_hv(env, SPR_HRMOR, "HRMOR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > 0x00000000); > > } > > > > @@ -7868,6 +7988,17 @@ static void gen_spr_power8_fscr(CPUPPCState > > *env) > > KVM_REG_PPC_FSCR, initval); > > } > > > > +static void gen_spr_power8_rpr(CPUPPCState *env) > > +{ > > +#if !defined(CONFIG_USER_ONLY) > > + spr_register_hv(env, SPR_RPR, "RPR", > > + SPR_NOACCESS, SPR_NOACCESS, > > + SPR_NOACCESS, SPR_NOACCESS, > > + &spr_read_generic, &spr_write_generic, > > + 0x00000103070F1F3F); > > +#endif > > +} > > + > > static void init_proc_book3s_64(CPUPPCState *env, int version) > > { > > gen_spr_ne_601(env); > > @@ -7919,9 +8050,12 @@ static void init_proc_book3s_64(CPUPPCState > > *env, int version) > > gen_spr_power8_pmu_user(env); > > gen_spr_power8_tm(env); > > gen_spr_vtb(env); > > + gen_spr_power8_rpr(env); > > } > > if (version < BOOK3S_CPU_POWER8) { > > gen_spr_book3s_dbg(env); > > + } else { > > + gen_spr_book3s_207_dbg(env); > > } > > #if !defined(CONFIG_USER_ONLY) > > switch (version) { >
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 30a03ce..c743eb1 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -1104,6 +1104,11 @@ static void gen_spr_amr (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_UAMOR, 0); + spr_register_hv(env, SPR_AMOR, "AMOR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0); #endif /* !CONFIG_USER_ONLY */ } #endif /* TARGET_PPC64 */ @@ -7490,6 +7495,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env) KVM_REG_PPC_DABRX, 0x00000000); } +static void gen_spr_book3s_207_dbg(CPUPPCState *env) +{ + spr_register_hv(env, SPR_DAWR, "DAWR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_DAWRX, "DAWRX", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + static void gen_spr_970_dbg(CPUPPCState *env) { /* Breakpoints */ @@ -7654,15 +7673,116 @@ static void gen_spr_power5p_lpar(CPUPPCState *env) spr_register_kvm(env, SPR_LPCR, "LPCR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_LPCR, 0x00000000); + KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); } +#if !defined(CONFIG_USER_ONLY) +static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) +{ + TCGv hmer = tcg_temp_new(); + + gen_load_spr(hmer, sprn); + tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); + gen_store_spr(sprn, hmer); + spr_store_dump_spr(sprn); + tcg_temp_free(hmer); +} +#endif + static void gen_spr_book3s_ids(CPUPPCState *env) { + /* FIXME: Will need to deal with thread vs core only SPRs */ + /* Processor identification */ - spr_register(env, SPR_PIR, "PIR", + spr_register_hv(env, SPR_PIR, "PIR", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, NULL, + 0x00000000); + spr_register_hv(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_TSCR, "TSCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HMER, "HMER", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_hmer, + 0x00000000); + spr_register_hv(env, SPR_HMEER, "HMEER", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_TFMR, "TFMR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_LPIDR, "LPIDR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HFSCR, "HFSCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_MMCRC, "MMCRC", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_MMCRH, "MMCRH", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HSPRG0, "HSPRG0", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HSPRG1, "HSPRG1", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HSRR0, "HSRR0", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HSRR1, "HSRR1", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HDAR, "HDAR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HDSISR, "HDSISR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_RMOR, "RMOR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HRMOR, "HRMOR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, 0x00000000); } @@ -7868,6 +7988,17 @@ static void gen_spr_power8_fscr(CPUPPCState *env) KVM_REG_PPC_FSCR, initval); } +static void gen_spr_power8_rpr(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + spr_register_hv(env, SPR_RPR, "RPR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000103070F1F3F); +#endif +} + static void init_proc_book3s_64(CPUPPCState *env, int version) { gen_spr_ne_601(env); @@ -7919,9 +8050,12 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) gen_spr_power8_pmu_user(env); gen_spr_power8_tm(env); gen_spr_vtb(env); + gen_spr_power8_rpr(env); } if (version < BOOK3S_CPU_POWER8) { gen_spr_book3s_dbg(env); + } else { + gen_spr_book3s_207_dbg(env); } #if !defined(CONFIG_USER_ONLY) switch (version) {
We don't give them a KVM reg number yet as no current KVM version supports HV mode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> --- target-ppc/translate_init.c | 140 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 137 insertions(+), 3 deletions(-)