From patchwork Fri Oct 30 15:00:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 538369 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DD56F140D92 for ; Sat, 31 Oct 2015 02:02:00 +1100 (AEDT) Received: from localhost ([::1]:51105 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBBm-0000cO-CT for incoming@patchwork.ozlabs.org; Fri, 30 Oct 2015 11:01:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42339) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBBH-00086F-C0 for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZsBBE-0001lY-0r for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:27 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:21117) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBBD-0001lS-SS for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:23 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 2A5A8849EB7D3 for ; Fri, 30 Oct 2015 15:01:20 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Fri, 30 Oct 2015 15:01:22 +0000 From: Leon Alrae To: Date: Fri, 30 Oct 2015 15:00:44 +0000 Message-ID: <1446217252-3637-2-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1446217252-3637-1-git-send-email-leon.alrae@imgtec.com> References: <1446217252-3637-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 1/9] target-mips: move the test for enabled interrupts to a separate function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Leon Alrae --- target-mips/cpu.c | 4 +++- target-mips/cpu.h | 29 +++++++++++++++-------------- target-mips/helper.c | 3 ++- 3 files changed, 20 insertions(+), 16 deletions(-) diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 37880d2..bbfee45 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -58,7 +58,9 @@ static bool mips_cpu_has_work(CPUState *cs) check for interrupts that can be taken. */ if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { - has_work = true; + if (cpu_mips_hw_interrupts_enabled(env)) { + has_work = true; + } } /* MIPS-MT has the ability to halt the CPU. */ diff --git a/target-mips/cpu.h b/target-mips/cpu.h index f32a0fd..3799d26 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -637,23 +637,24 @@ static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) return env->hflags & MIPS_HFLAG_KSU; } -static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { - int32_t pending; - int32_t status; - int r; - - if (!(env->CP0_Status & (1 << CP0St_IE)) || - (env->CP0_Status & (1 << CP0St_EXL)) || - (env->CP0_Status & (1 << CP0St_ERL)) || + return (env->CP0_Status & (1 << CP0St_IE)) && + !(env->CP0_Status & (1 << CP0St_EXL)) && + !(env->CP0_Status & (1 << CP0St_ERL)) && + !(env->hflags & MIPS_HFLAG_DM) && /* Note that the TCStatus IXMT field is initialized to zero, and only MT capable cores can set it to one. So we don't need to check for MT capabilities here. */ - (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) || - (env->hflags & MIPS_HFLAG_DM)) { - /* Interrupts are disabled */ - return 0; - } + !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); +} + +/* Check if there is pending and not masked out interrupt */ +static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) +{ + int32_t pending; + int32_t status; + bool r; pending = env->CP0_Cause & CP0Ca_IP_mask; status = env->CP0_Status & CP0Ca_IP_mask; @@ -667,7 +668,7 @@ static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) /* A MIPS configured with compatibility or VInt (Vectored Interrupts) treats the pending lines as individual interrupt lines, the status lines are individual masks. */ - r = pending & status; + r = (pending & status) != 0; } return r; } diff --git a/target-mips/helper.c b/target-mips/helper.c index 01c4461..2d86323 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -759,7 +759,8 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; - if (cpu_mips_hw_interrupts_pending(env)) { + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { /* Raise it */ cs->exception_index = EXCP_EXT_INTERRUPT; env->error_code = 0;