From patchwork Tue Oct 27 14:33:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 536663 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 189611401DA for ; Wed, 28 Oct 2015 01:44:10 +1100 (AEDT) Received: from localhost ([::1]:60127 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr5Tr-0003Vk-Gz for incoming@patchwork.ozlabs.org; Tue, 27 Oct 2015 10:44:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr5Jf-0001VW-RQ for qemu-devel@nongnu.org; Tue, 27 Oct 2015 10:33:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zr5Jb-0007TQ-Gx for qemu-devel@nongnu.org; Tue, 27 Oct 2015 10:33:35 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35203) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr5Jb-0007SU-9z for qemu-devel@nongnu.org; Tue, 27 Oct 2015 10:33:31 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Zr5Ja-0000Vz-Vp for qemu-devel@nongnu.org; Tue, 27 Oct 2015 14:33:30 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 27 Oct 2015 14:33:29 +0000 Message-Id: <1445956409-1818-28-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1445956409-1818-1-git-send-email-peter.maydell@linaro.org> References: <1445956409-1818-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 27/27] target-arm: Add support for S1 + S2 MMU translations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias Message-id: 1445864527-14520-15-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target-arm/helper.c | 38 +++++++++++++++++++++++++++++++------- target-arm/op_helper.c | 1 + 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index eb9a00d..1966f9c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -7196,14 +7196,38 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, ARMMMUFaultInfo *fi) { if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { - /* TODO: when we support EL2 we should here call ourselves recursively - * to do the stage 1 and then stage 2 translations. The arm_ld*_ptw - * functions will also need changing to perform ARMMMUIdx_S2NS loads - * rather than direct physical memory loads when appropriate. - * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. + /* Call ourselves recursively to do the stage 1 and then stage 2 + * translations. */ - assert(!arm_feature(env, ARM_FEATURE_EL2)); - mmu_idx += ARMMMUIdx_S1NSE0; + if (arm_feature(env, ARM_FEATURE_EL2)) { + hwaddr ipa; + int s2_prot; + int ret; + + ret = get_phys_addr(env, address, access_type, + mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs, + prot, page_size, fsr, fi); + + /* If S1 fails or S2 is disabled, return early. */ + if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { + *phys_ptr = ipa; + return ret; + } + + /* S1 is done. Now do S2 translation. */ + ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, + phys_ptr, attrs, &s2_prot, + page_size, fsr, fi); + fi->s2addr = ipa; + /* Combine the S1 and S2 perms. */ + *prot &= s2_prot; + return ret; + } else { + /* + * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. + */ + mmu_idx += ARMMMUIdx_S1NSE0; + } } /* The page table entries may downgrade secure to non-secure, but diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 333078a..a4c4ebf 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -101,6 +101,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, target_el = exception_target_el(env); if (fi.stage2) { target_el = 2; + env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; } same_el = arm_current_el(env) == target_el; /* AArch64 syndrome does not have an LPAE bit */