From patchwork Wed Oct 21 21:42:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 534096 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 857C414076E for ; Thu, 22 Oct 2015 08:46:10 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=JqZaMfa3; dkim-atps=neutral Received: from localhost ([::1]:54544 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zp1Cy-0003By-HM for incoming@patchwork.ozlabs.org; Wed, 21 Oct 2015 17:46:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zp1Ap-0000zB-HB for qemu-devel@nongnu.org; Wed, 21 Oct 2015 17:43:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zp1Ao-0001P2-G9 for qemu-devel@nongnu.org; Wed, 21 Oct 2015 17:43:55 -0400 Received: from mail-qg0-x230.google.com ([2607:f8b0:400d:c04::230]:36825) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zp1Ao-0001Oy-C7 for qemu-devel@nongnu.org; Wed, 21 Oct 2015 17:43:54 -0400 Received: by qgad10 with SMTP id d10so40182144qga.3 for ; Wed, 21 Oct 2015 14:43:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=u9aZnYavvfmWpi7An7VmCKJFkcCkBJu6tKQ371Uuf5U=; b=JqZaMfa3x8Flwn/COz9+cTS7ae3+n8me5EnY55AOqGO9N0j2hLjgWlgvDCOsAmheH6 FNvrWDBhyrqwh0upI9xoWlfvrldHmo4Gj/WrSi4KLkwHw6n9uDVgiwkLIefkJwOeF/Ek l0EiRBr9pkeUh/mI7cluX4Wpb8yZUdZuLG/SFdrOyeSAqwGQwu9cVPZkg0Lp5R1PXgbE tosA3mXPyNYBlfOxS3e+SlUq0SHvAx26wtPC20KR6zke5O/rh9gRGdcdWQMQvrXTzVwG bdYAOmy8YEDe38G1zyCKNYSPEsm4m0UCJAUGBSRCpLojYfTItGgJX8JleOZ501ezv+gd zt8g== X-Received: by 10.140.146.13 with SMTP id 13mr15063294qhs.1.1445463834121; Wed, 21 Oct 2015 14:43:54 -0700 (PDT) Received: from bigtime.com (cpe-50-113-10-46.hawaii.res.rr.com. [50.113.10.46]) by smtp.gmail.com with ESMTPSA id n48sm4071482qgd.35.2015.10.21.14.43.51 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 21 Oct 2015 14:43:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 21 Oct 2015 11:42:55 -1000 Message-Id: <1445463779-5823-7-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1445463779-5823-1-git-send-email-rth@twiddle.net> References: <1445463779-5823-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c04::230 Cc: peter.maydell@linaro.org, James Hogan Subject: [Qemu-devel] [PULL 06/10] tcg/mips: Add use_mips32r6_instructions definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: James Hogan Add definition use_mips32r6_instructions to the MIPS TCG backend which is constant 1 when built for MIPS release 6. This will be used to decide between pre-R6 and R6 instruction encodings. Reviewed-by: Aurelien Jarno Signed-off-by: James Hogan Signed-off-by: Richard Henderson Message-Id: <1443788657-14537-4-git-send-email-james.hogan@imgtec.com> --- tcg/mips/tcg-target.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index f5ba52c..e579c10 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -96,6 +96,13 @@ extern bool use_mips32_instructions; extern bool use_mips32r2_instructions; #endif +/* MIPS32R6 instruction set detection */ +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 6) +#define use_mips32r6_instructions 1 +#else +#define use_mips32r6_instructions 0 +#endif + /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_rem_i32 1