From patchwork Tue Oct 6 17:49:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 527020 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:4830:134:3::10]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AEF451402A2 for ; Wed, 7 Oct 2015 09:00:11 +1100 (AEDT) Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZjWP1-0006QN-Jn for incoming@patchwork.ozlabs.org; Tue, 06 Oct 2015 13:52:41 -0400 X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on eggs.gnu.org X-Spam-Level: X-Spam-Status: No, score=0.8 required=5.0 tests=BAYES_50 autolearn=disabled version=3.3.2 Received: from lists.gnu.org ([208.118.235.17]:43317) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjWP1-0006Or-Aq for incoming@patchwork.ozlabs.org; Tue, 06 Oct 2015 13:51:51 -0400 Received: from localhost ([::1]:52983 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjWOf-00069T-U9 for incoming@patchwork.ozlabs.org; Tue, 06 Oct 2015 13:51:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40484) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjWO2-0005Vl-AI for qemu-devel@nongnu.org; Tue, 06 Oct 2015 13:51:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZjWNG-0006j6-3K for qemu-devel@nongnu.org; Tue, 06 Oct 2015 13:50:50 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56030) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjWNF-0006h7-NM for qemu-devel@nongnu.org; Tue, 06 Oct 2015 13:50:01 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 26DB81418CB; Tue, 6 Oct 2015 17:50:01 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 13EB51418CD; Tue, 6 Oct 2015 17:50:01 +0000 (UTC) Received: from keeshans.qualcomm.com (rrcs-67-52-130-30.west.biz.rr.com [67.52.130.30]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 603F11418C7; Tue, 6 Oct 2015 17:49:59 +0000 (UTC) From: Christopher Covington To: drjones@redhat.com, qemu-devel@nongnu.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, wei@redhat.com Date: Tue, 6 Oct 2015 13:49:24 -0400 Message-Id: <1444153766-12532-2-git-send-email-cov@codeaurora.org> X-Mailer: git-send-email 1.8.1.1 In-Reply-To: <1444153766-12532-1-git-send-email-cov@codeaurora.org> References: <5612EDA5.9010506@redhat.com> <1444153766-12532-1-git-send-email-cov@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x Cc: alindsay@codeaurora.org, croberts@codeaurora.org, Christopher Covington , shannon.zhao@linaro.org, alistair.francis@xilinx.com Subject: [Qemu-devel] [kvm-unit-tests PATCHv3 1/3] arm: Add PMU test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 208.118.235.17 Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington --- arm/pmu.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 5 ++++ config/config-arm64.mak | 4 ++- 3 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 arm/pmu.c diff --git a/arm/pmu.c b/arm/pmu.c new file mode 100644 index 0000000..91a3688 --- /dev/null +++ b/arm/pmu.c @@ -0,0 +1,66 @@ +/* + * Test the ARM Performance Monitors Unit (PMU). + * + * Copyright 2015 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License version 2.1 and + * only version 2.1 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License + * for more details. + */ +#include "libcflat.h" + +struct pmu_data { + union { + uint32_t pmcr_el0; + struct { + uint32_t enable:1; + uint32_t event_counter_reset:1; + uint32_t cycle_counter_reset:1; + uint32_t cycle_counter_clock_divider:1; + uint32_t event_counter_export:1; + uint32_t cycle_counter_disable_when_prohibited:1; + uint32_t cycle_counter_long:1; + uint32_t zeros:4; + uint32_t num_counters:5; + uint32_t identification_code:8; + uint32_t implementer:8; + }; + }; +}; + +/* As a simple sanity check on the PMCR_EL0, ensure the implementer field isn't + * null. Also print out a couple other interesting fields for diagnostic + * purposes. For example, as of fall 2015, QEMU TCG mode doesn't implement + * event counters and therefore reports zero of them, but hopefully support for + * at least the instructions event will be added in the future and the reported + * number of event counters will become nonzero. + */ +static bool check_pmcr(void) +{ + struct pmu_data pmcr; + + asm volatile("mrs %0, pmcr_el0" : "=r" (pmcr)); + + printf("PMU implementer: %c\n", pmcr.implementer); + printf("Identification code: 0x%x\n", pmcr.identification_code); + printf("Event counters: %d\n", pmcr.num_counters); + + if (pmcr.implementer) + return true; + + return false; +} + +int main(void) +{ + report_prefix_push("pmu"); + + report("Control register", check_pmcr()); + + return report_summary(); +} diff --git a/arm/unittests.cfg b/arm/unittests.cfg index e068a0c..fd94adb 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -35,3 +35,8 @@ file = selftest.flat smp = `getconf _NPROCESSORS_CONF` extra_params = -append 'smp' groups = selftest + +# Test PMU support without -icount +[pmu] +file = pmu.flat +groups = pmu diff --git a/config/config-arm64.mak b/config/config-arm64.mak index d61b703..140b611 100644 --- a/config/config-arm64.mak +++ b/config/config-arm64.mak @@ -12,9 +12,11 @@ cflatobjs += lib/arm64/processor.o cflatobjs += lib/arm64/spinlock.o # arm64 specific tests -tests = +tests = $(TEST_DIR)/pmu.flat include config/config-arm-common.mak arch_clean: arm_clean $(RM) lib/arm64/.*.d + +$(TEST_DIR)/pmu.elf: $(cstart.o) $(TEST_DIR)/pmu.o