From patchwork Sun Oct 4 11:01:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 526094 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A0D5E1402C4 for ; Sun, 4 Oct 2015 22:04:37 +1100 (AEDT) Received: from localhost ([::1]:42026 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zih5n-00055f-Sf for incoming@patchwork.ozlabs.org; Sun, 04 Oct 2015 07:04:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55275) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zih3F-0000jc-Jz for qemu-devel@nongnu.org; Sun, 04 Oct 2015 07:01:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zih3C-00075H-Es for qemu-devel@nongnu.org; Sun, 04 Oct 2015 07:01:57 -0400 Received: from smtpbg64.qq.com ([103.7.28.238]:25213) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zih3B-00074P-T3 for qemu-devel@nongnu.org; Sun, 04 Oct 2015 07:01:54 -0400 X-QQ-mid: esmtp23t1443956500t921t27481 Received: from localhost.localdomain.localdoma (unknown [223.72.67.84]) by esmtp4.qq.com (ESMTP) with id ; Sun, 04 Oct 2015 19:01:37 +0800 (CST) X-QQ-SSF: 01000000000000F0FH800F00002000G X-QQ-FEAT: Gf8h89u9tNyx+OIDAyQVu9X+H1khnzPRVDo5VqaUtGQKkFVsORkdFv9L/Hf04 ywMYVo71wQdMBCTusdI5oVQj4vCKdAgATnAyATYQfL4KjlyWimwBiWB0yzoVZmkXGJ4VwCa 861h9bKInWiGikwi/oFYe8ldQUju+7x/LCkZU5pO6nDqtN92T+lQ0lVE5uJG6BVixGFFqrW o/M7uNXwJEogxBLDo2Di7BQzn6SKa6Lc6/qvyS39/cVKDseDIqLoe X-QQ-GoodBg: 0 X-QQ-CSender: gang.chen.5i5j@qq.com From: gang.chen.5i5j@gmail.com To: peter.maydell@linaro.org, rth@twiddle.net Date: Sun, 4 Oct 2015 19:01:26 +0800 Message-Id: <1443956491-26850-2-git-send-email-gang.chen.5i5j@gmail.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1443956491-26850-1-git-send-email-gang.chen.5i5j@gmail.com> References: <1443956491-26850-1-git-send-email-gang.chen.5i5j@gmail.com> X-QQ-SENDSIZE: 520 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 103.7.28.238 Cc: cmetcalf@ezchip.com, qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com, Chen Gang Subject: [Qemu-devel] [PATCH v2] target-tilegx: Implement v?int_* instructions. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Chen Gang Signed-off-by: Chen Gang --- target-tilegx/helper.h | 5 ++++ target-tilegx/simd_helper.c | 56 +++++++++++++++++++++++++++++++++++++++++++++ target-tilegx/translate.c | 14 ++++++++++++ 3 files changed, 75 insertions(+) diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h index 82d84f1..c58ee20 100644 --- a/target-tilegx/helper.h +++ b/target-tilegx/helper.h @@ -10,6 +10,11 @@ DEF_HELPER_FLAGS_3(cmula, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(cmulaf, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_4(cmul2, TCG_CALL_NO_RWG_SE, i64, i64, i64, int, int) +DEF_HELPER_FLAGS_2(v1int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v1int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64) + DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c index 23c20bd..6fa6318 100644 --- a/target-tilegx/simd_helper.c +++ b/target-tilegx/simd_helper.c @@ -102,3 +102,59 @@ uint64_t helper_v2shrs(uint64_t a, uint64_t b) } return r; } + +uint64_t helper_v1int_h(uint64_t a, uint64_t b) +{ + uint64_t r = 0, tmp; + int i; + + for (i = 0; i < 32; i += 8) { + tmp = (uint8_t)(a >> (i + 32)); + r |= tmp << (2 * i + 8); + tmp = (uint8_t)(b >> (i + 32)); + r |= tmp << 2 * i; + } + return r; +} + +uint64_t helper_v1int_l(uint64_t a, uint64_t b) +{ + uint64_t r = 0, tmp; + int i; + + for (i = 0; i < 32; i += 8) { + tmp = (uint8_t)(a >> i); + r |= tmp << (2 * i + 8); + tmp = (uint8_t)(b >> i); + r |= tmp << 2 * i; + } + return r; +} + +uint64_t helper_v2int_h(uint64_t a, uint64_t b) +{ + uint64_t r = 0, tmp; + int i; + + for (i = 0; i < 32; i += 16) { + tmp = (uint16_t)(a >> (i + 32)); + r |= tmp << (2 * i + 16); + tmp = (uint16_t)(b >> (i + 32)); + r |= tmp << 2 * i; + } + return r; +} + +uint64_t helper_v2int_l(uint64_t a, uint64_t b) +{ + uint64_t r = 0, tmp; + int i; + + for (i = 0; i < 32; i += 16) { + tmp = (uint16_t)(a >> i); + r |= tmp << (2 * i + 16); + tmp = (uint16_t)(b >> i); + r |= tmp << 2 * i; + } + return r; +} diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 9bb8857..034cbc2 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -1260,10 +1260,17 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(V1DOTPUS, 0, X0): case OE_RRR(V1DOTPU, 0, X0): case OE_RRR(V1DOTP, 0, X0): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V1INT_H, 0, X0): case OE_RRR(V1INT_H, 0, X1): + gen_helper_v1int_h(tdest, tsrca, tsrcb); + mnemonic = "v1int_h"; + break; case OE_RRR(V1INT_L, 0, X0): case OE_RRR(V1INT_L, 0, X1): + gen_helper_v1int_l(tdest, tsrca, tsrcb); + mnemonic = "v1int_l"; + break; case OE_RRR(V1MAXU, 0, X0): case OE_RRR(V1MAXU, 0, X1): case OE_RRR(V1MINU, 0, X0): @@ -1329,10 +1336,17 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(V2CMPNE, 0, X1): case OE_RRR(V2DOTPA, 0, X0): case OE_RRR(V2DOTP, 0, X0): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V2INT_H, 0, X0): case OE_RRR(V2INT_H, 0, X1): + gen_helper_v2int_h(tdest, tsrca, tsrcb); + mnemonic = "v2int_h"; + break; case OE_RRR(V2INT_L, 0, X0): case OE_RRR(V2INT_L, 0, X1): + gen_helper_v2int_l(tdest, tsrca, tsrcb); + mnemonic = "v2int_l"; + break; case OE_RRR(V2MAXS, 0, X0): case OE_RRR(V2MAXS, 0, X1): case OE_RRR(V2MINS, 0, X0):