From patchwork Wed Sep 30 15:30:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 524826 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5D5DB140D68 for ; Thu, 1 Oct 2015 17:18:42 +1000 (AEST) Received: from localhost ([::1]:39560 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhY8V-00025I-R8 for incoming@patchwork.ozlabs.org; Thu, 01 Oct 2015 03:18:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhJab-0002XC-Pm for qemu-devel@nongnu.org; Wed, 30 Sep 2015 11:46:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZhJaX-0007Li-H4 for qemu-devel@nongnu.org; Wed, 30 Sep 2015 11:46:41 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:62264) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhJaX-0007LT-BE for qemu-devel@nongnu.org; Wed, 30 Sep 2015 11:46:37 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 9E89FD3675DCC; Wed, 30 Sep 2015 16:30:38 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 30 Sep 2015 16:30:41 +0100 Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Wed, 30 Sep 2015 16:30:41 +0100 From: James Hogan To: Date: Wed, 30 Sep 2015 16:30:26 +0100 Message-ID: <1443627027-2193-7-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 2.4.9 In-Reply-To: <1443627027-2193-1-git-send-email-james.hogan@imgtec.com> References: <1443627027-2193-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: James Hogan , Leon Alrae , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH 6/7] tcg/mips: Support full movcond select operation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Adapt the MIPS movcond implementation to handle the full select operation using a pair of MOVN/MOVZ instructions. This allows the register alias constraint to be removed (which is what ensured v2 == dest), and allows it to be more easily extended to support the MIPS r6 instructions SELNEZ/SELEQZ which replace MOVN/MOVZ and require similar logic. For example, previously we only supported: movcond_i32 dest, c1, c2, v1, v2=dest, cond With the host code: MOV[ZN] dest, v1, [!](c1 cond c2) Meaning: if (c1 cond c2) dest = v1; But now v2 doesn't have to equal dest, so we can support: movcond_i32 dest, c1, c2, v1, v2, cond With the host code: #if dest != v1 MOV[ZN] dest, v1, [!](c1 cond c2) #endif #if dest != v2 MOV[NZ] dest, v1, ![!](c1 cond c2) #endif Meaning: #if dest != v1 if ([!](c1 cond c2)) dest = v1; #endif #if dest != v2 if (![!](c1 cond c2)) dest = v2; #endif Impact/benefit of this patch on TB average host size for a MIPr6 guest kernel boot was negligible, so it was considered preferable to ifdef'ing the constraint based on the presence of MIPS r6. Signed-off-by: James Hogan Cc: Richard Henderson Cc: Aurelien Jarno --- tcg/mips/tcg-target.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index c447db6011ea..9849896bd75b 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -852,13 +852,17 @@ static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, } static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg c1, TCGReg c2, TCGReg v) + TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) { - MIPSInsn m_opc = OPC_MOVN; + MIPSInsn m_opc_t = OPC_MOVN; + MIPSInsn m_opc_f = OPC_MOVZ; + const MIPSInsn m_opc_t_inv = m_opc_f; + const MIPSInsn m_opc_f_inv = m_opc_t; switch (cond) { case TCG_COND_EQ: - m_opc = OPC_MOVZ; + m_opc_t = m_opc_t_inv; + m_opc_f = m_opc_f_inv; /* FALLTHRU */ case TCG_COND_NE: if (c2 != 0) { @@ -871,14 +875,20 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, /* Minimize code size by preferring a compare not requiring INV. */ if (mips_cmp_map[cond] & MIPS_CMP_INV) { cond = tcg_invert_cond(cond); - m_opc = OPC_MOVZ; + m_opc_t = m_opc_t_inv; + m_opc_f = m_opc_f_inv; } tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); c1 = TCG_TMP0; break; } - tcg_out_opc_reg(s, m_opc, ret, v, c1); + if (v1 != ret) { + tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); + } + if (v2 != ret) { + tcg_out_opc_reg(s, m_opc_f, ret, v2, c1); + } } static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) @@ -1575,7 +1585,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_movcond_i32: - tcg_out_movcond(s, args[5], a0, a1, a2, args[3]); + tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); break; case INDEX_op_setcond_i32: @@ -1664,7 +1674,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, { INDEX_op_brcond_i32, { "rZ", "rZ" } }, - { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } }, + { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "rZ" } }, { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },