From patchwork Wed Sep 30 05:09:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 524721 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E168F1402B6 for ; Thu, 1 Oct 2015 14:41:29 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=QN/FSese; dkim-atps=neutral Received: from localhost ([::1]:37597 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhVgN-0006PO-Cp for incoming@patchwork.ozlabs.org; Thu, 01 Oct 2015 00:41:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56305) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zh9fK-00023C-Ml for qemu-devel@nongnu.org; Wed, 30 Sep 2015 01:10:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zh9fF-0004p6-Se for qemu-devel@nongnu.org; Wed, 30 Sep 2015 01:10:54 -0400 Received: from mail-pa0-x230.google.com ([2607:f8b0:400e:c03::230]:33539) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zh9fF-0004oz-KM for qemu-devel@nongnu.org; Wed, 30 Sep 2015 01:10:49 -0400 Received: by pacex6 with SMTP id ex6so28393012pac.0 for ; Tue, 29 Sep 2015 22:10:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=onCcnZj5r0AFQM4w+EvTqO7npoTcMMWoTVnUAW4Uz6A=; b=QN/FSese8nAjVe3BrNosUeiL4V0vBNRnnpIuOSm/ua54M4D1NeGbKcYNeyPQC+mWot RE2DS7i4+ZpSUS6l7hipGX3mWBtEBydZvkd73aViwFaCyOCOScOoyq3xiY/eTF0fvItC +8TXWDZDQ5cpKJmRoHOdK2nA0vTrv0hdgFMFsrGvAhh3Evlh7PFWs3OzbB9NkPlwgtCd jsJb7iz2hrLXat4PB98xZtEMHrQyFO///afvYY9usaH5mCGi2Pjo0PZv/OooT+rzU7YM ZZqBmT8CL6vuRtQKW3dCLCLcqhEEbP0uDJ2onZBxUizoITx3NE+WdhPqerXQTLsyMoYG fDvA== X-Received: by 10.66.150.105 with SMTP id uh9mr2450888pab.78.1443589849128; Tue, 29 Sep 2015 22:10:49 -0700 (PDT) Received: from bigtime.com ([1.144.36.49]) by smtp.gmail.com with ESMTPSA id w9sm28763437pbt.29.2015.09.29.22.10.46 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Sep 2015 22:10:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 30 Sep 2015 15:09:23 +1000 Message-Id: <1443589786-26929-4-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1443589786-26929-1-git-send-email-rth@twiddle.net> References: <1443589786-26929-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::230 Cc: peter.maydell@linaro.org, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v4 03/26] target-*: Increment num_insns immediately after tcg_gen_insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-alpha/translate.c | 4 ++-- target-arm/translate-a64.c | 6 +++--- target-arm/translate.c | 7 ++++--- target-cris/translate.c | 4 ++-- target-i386/translate.c | 5 +++-- target-lm32/translate.c | 5 ++--- target-m68k/translate.c | 4 ++-- target-microblaze/translate.c | 5 +++-- target-mips/translate.c | 5 ++--- target-moxie/translate.c | 2 +- target-openrisc/translate.c | 4 ++-- target-ppc/translate.c | 4 ++-- target-s390x/translate.c | 3 ++- target-sh4/translate.c | 4 ++-- target-sparc/translate.c | 4 ++-- target-tilegx/translate.c | 3 ++- target-tricore/translate.c | 3 +-- target-unicore32/translate.c | 4 ++-- target-xtensa/translate.c | 4 ++-- 19 files changed, 41 insertions(+), 39 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 60370d6..fa0ac2d 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -2934,12 +2934,12 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(ctx.pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } insn = cpu_ldl_code(env, ctx.pc); - num_insns++; TCGV_UNUSED_I64(ctx.zero); TCGV_UNUSED_I64(ctx.sink); diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 6a66ac0..4670941 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11104,8 +11104,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -11120,7 +11121,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns == 0); + assert(num_insns == 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); dc->is_jmp = DISAS_EXC; @@ -11139,7 +11140,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - num_insns++; } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && diff --git a/target-arm/translate.c b/target-arm/translate.c index 8348848..cd88997 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11349,9 +11349,11 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); + } if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. @@ -11364,7 +11366,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns == 0); + assert(num_insns == 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); goto done_generating; @@ -11400,7 +11402,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, * Otherwise the subsequent code could get translated several times. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - num_insns ++; } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && diff --git a/target-cris/translate.c b/target-cris/translate.c index 0a4b363..bba7217 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3194,11 +3194,12 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } dc->clear_x = 1; @@ -3210,7 +3211,6 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, cris_clear_x_flag(dc); } - num_insns++; /* Check for delayed branches here. If we do it before actually generating any host code, the simulator will just loop doing nothing for on this program location. */ diff --git a/target-i386/translate.c b/target-i386/translate.c index 82d32e1..3d0c23d 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7960,12 +7960,13 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(pc_ptr); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); + } pc_ptr = disas_insn(env, dc, pc_ptr); - num_insns++; /* stop translation if indicated */ if (dc->is_jmp) break; diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 84eeac3..a34914a 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1103,18 +1103,17 @@ void gen_intermediate_code_internal(LM32CPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } decode(dc, cpu_ldl_code(env, dc->pc)); dc->pc += 4; - num_insns++; - } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled diff --git a/target-m68k/translate.c b/target-m68k/translate.c index bfd9c00..422244e 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3022,14 +3022,14 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } dc->insn_pc = dc->pc; disas_m68k_insn(env, dc); - num_insns++; } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 02ccf45..a25b042 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1715,19 +1715,20 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); + } dc->clear_imm = 1; decode(dc, cpu_ldl_code(env, dc->pc)); if (dc->clear_imm) dc->tb_flags &= ~IMM_FLAG; dc->pc += 4; - num_insns++; if (dc->delayed_branch) { dc->delayed_branch--; diff --git a/target-mips/translate.c b/target-mips/translate.c index aa0e0fd..66147d8 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19619,8 +19619,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(ctx.pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -19659,8 +19660,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, } ctx.pc += insn_bytes; - num_insns++; - /* Execute a branch and its delay slot as a single instruction. This is what GDB expects and is consistent with what the hardware does (e.g. if a delay slot instruction faults, the diff --git a/target-moxie/translate.c b/target-moxie/translate.c index 1becfde..f71ed24 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -862,10 +862,10 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(ctx.pc); + num_insns++; ctx.opcode = cpu_lduw_code(env, ctx.pc); ctx.pc += decode_opc(cpu, &ctx); - num_insns++; if (cs->singlestep_enabled) { break; diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 4f9b768..f9b4ed5 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1688,8 +1688,9 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, tcg_ctx.gen_opc_icount[k] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } dc->ppc = dc->pc - 4; @@ -1698,7 +1699,6 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, tcg_gen_movi_tl(cpu_npc, dc->npc); disas_openrisc_insn(dc, cpu); dc->pc = dc->npc; - num_insns++; /* delay slot */ if (dc->delayed_branch) { dc->delayed_branch--; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 6ca3e9f..7c288aa 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11503,11 +11503,12 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(ctx.nip); + num_insns++; LOG_DISAS("----------------\n"); LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", ctx.nip, ctx.mem_idx, (int)msr_ir); - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); if (unlikely(need_byteswap(&ctx))) { ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); @@ -11519,7 +11520,6 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); ctx.nip += 4; table = env->opcodes; - num_insns++; handler = table[opc1(ctx.opcode)]; if (is_indirect_opcode(handler)) { table = ind_table(handler); diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 2767f6a..58cf365 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5371,8 +5371,9 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc.pc); + num_insns++; - if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 1e43e6d..e0294e7 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1873,14 +1873,14 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_icount[ii] = num_insns; } tcg_gen_insn_start(ctx.pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } ctx.opcode = cpu_lduw_code(env, ctx.pc); decode_opc(&ctx); - num_insns++; ctx.pc += 2; if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) break; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index a47e65f..762eb9b 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5268,8 +5268,9 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, } } tcg_gen_insn_start(dc->pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -5277,7 +5278,6 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, insn = cpu_ldl_code(env, dc->pc); disas_sparc_insn(dc, insn); - num_insns++; if (dc->is_br) break; diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 6babc3c..c23b761 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -2097,6 +2097,7 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; translate_one_bundle(dc, cpu_ldq_data(env, dc->pc)); @@ -2105,7 +2106,7 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu, break; } dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES; - if (++num_insns >= max_insns + if (num_insns >= max_insns || dc->pc >= next_page_start || tcg_op_buf_full()) { /* Ending the TB due to TB size or page boundary. Set PC. */ diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 27564d3..fa10d5c 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -8293,12 +8293,11 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb, gen_tb_start(tb); while (ctx.bstate == BS_NONE) { tcg_gen_insn_start(ctx.pc); + num_insns++; ctx.opcode = cpu_ldl_code(env, ctx.pc); decode_opc(env, &ctx, 0); - num_insns++; - if (tcg_op_buf_full()) { gen_save_pc(ctx.next_pc); tcg_gen_exit_tb(0); diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 28db34a..7aad61f 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1938,8 +1938,9 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -1958,7 +1959,6 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, * Otherwise the subsequent code could get translated several times. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - num_insns++; } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index ab9e8f9..3607e41 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -3077,10 +3077,11 @@ void gen_intermediate_code_internal(XtensaCPU *cpu, tcg_ctx.gen_opc_icount[lj] = insn_count; } tcg_gen_insn_start(dc.pc); + ++insn_count; ++dc.ccount_delta; - if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -3101,7 +3102,6 @@ void gen_intermediate_code_internal(XtensaCPU *cpu, } disas_xtensa_insn(env, &dc); - ++insn_count; if (dc.icount) { tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); }