@@ -97,6 +97,7 @@
struct arm_boot_info;
#define NB_MMU_MODES 7
+#define TARGET_INSN_START_EXTRA_WORDS 1
/* We currently assume float and double are IEEE single and double
precision respectively.
@@ -11090,7 +11090,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
tcg_ctx.gen_opc_instr_start[lj] = 1;
tcg_ctx.gen_opc_icount[lj] = num_insns;
}
- tcg_gen_insn_start(dc->pc);
+ tcg_gen_insn_start(dc->pc, 0);
num_insns++;
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
@@ -11317,7 +11317,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
tcg_ctx.gen_opc_instr_start[lj] = 1;
tcg_ctx.gen_opc_icount[lj] = num_insns;
}
- tcg_gen_insn_start(dc->pc);
+ tcg_gen_insn_start(dc->pc,
+ (dc->condexec_cond << 4) | (dc->condexec_mask >> 1));
num_insns++;
#ifdef CONFIG_USER_ONLY