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[50.194.63.110]) by smtp.gmail.com with ESMTPSA id 20sm1948550ioj.25.2015.09.22.13.25.59 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Sep 2015 13:25:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 22 Sep 2015 13:24:59 -0700 Message-Id: <1442953507-4074-18-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1442953507-4074-1-git-send-email-rth@twiddle.net> References: <1442953507-4074-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4001:c06::22b Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v3 17/25] target-*: Drop cpu_gen_code define X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This symbol no longer exists. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- target-alpha/cpu.h | 1 - target-arm/cpu.h | 1 - target-cris/cpu.h | 1 - target-i386/cpu.h | 1 - target-lm32/cpu.h | 1 - target-m68k/cpu.h | 1 - target-microblaze/cpu.h | 1 - target-mips/cpu.h | 1 - target-moxie/cpu.h | 1 - target-openrisc/cpu.h | 1 - target-ppc/cpu.h | 1 - target-s390x/cpu.h | 1 - target-sh4/cpu.h | 1 - target-sparc/cpu.h | 1 - target-tilegx/cpu.h | 1 - target-xtensa/cpu.h | 1 - 16 files changed, 16 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index ef88ffb..ce074fa 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -289,7 +289,6 @@ struct CPUAlphaState { #define cpu_list alpha_cpu_list #define cpu_exec cpu_alpha_exec -#define cpu_gen_code cpu_alpha_gen_code #define cpu_signal_handler cpu_alpha_signal_handler #include "exec/cpu-all.h" diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c4a7400..21f90e4 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1603,7 +1603,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model)) #define cpu_exec cpu_arm_exec -#define cpu_gen_code cpu_arm_gen_code #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 8ae7708..99dd90e 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -225,7 +225,6 @@ enum { #define cpu_init(cpu_model) CPU(cpu_cris_init(cpu_model)) #define cpu_exec cpu_cris_exec -#define cpu_gen_code cpu_cris_gen_code #define cpu_signal_handler cpu_cris_signal_handler /* MMU modes definitions */ diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 717d558..280d5f2 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1190,7 +1190,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model)) #define cpu_exec cpu_x86_exec -#define cpu_gen_code cpu_x86_gen_code #define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list #define cpudef_setup x86_cpudef_setup diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index cc77263..d40b9f7 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -221,7 +221,6 @@ bool lm32_cpu_do_semihosting(CPUState *cs); #define cpu_list lm32_cpu_list #define cpu_exec cpu_lm32_exec -#define cpu_gen_code cpu_lm32_gen_code #define cpu_signal_handler cpu_lm32_signal_handler int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index 43a9a1c..705a3f9 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -215,7 +215,6 @@ void register_m68k_insns (CPUM68KState *env); #define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model)) #define cpu_exec cpu_m68k_exec -#define cpu_gen_code cpu_m68k_gen_code #define cpu_signal_handler cpu_m68k_signal_handler #define cpu_list m68k_cpu_list diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 402124a..e05e6ad 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -297,7 +297,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, #define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model)) #define cpu_exec cpu_mb_exec -#define cpu_gen_code cpu_mb_gen_code #define cpu_signal_handler cpu_mb_signal_handler /* MMU modes definitions */ diff --git a/target-mips/cpu.h b/target-mips/cpu.h index fd23832..77ff614 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -622,7 +622,6 @@ void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); #define cpu_exec cpu_mips_exec -#define cpu_gen_code cpu_mips_gen_code #define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h index 15ca15b..821bfee 100644 --- a/target-moxie/cpu.h +++ b/target-moxie/cpu.h @@ -124,7 +124,6 @@ int cpu_moxie_signal_handler(int host_signum, void *pinfo, #define cpu_init(cpu_model) CPU(cpu_moxie_init(cpu_model)) #define cpu_exec cpu_moxie_exec -#define cpu_gen_code cpu_moxie_gen_code #define cpu_signal_handler cpu_moxie_signal_handler static inline int cpu_mmu_index(CPUMoxieState *env, bool ifetch) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 560210d9..952ebba 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -361,7 +361,6 @@ int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_list cpu_openrisc_list #define cpu_exec cpu_openrisc_exec -#define cpu_gen_code cpu_openrisc_gen_code #define cpu_signal_handler cpu_openrisc_signal_handler #ifndef CONFIG_USER_ONLY diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 406d308..2d527e5 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1241,7 +1241,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model)) #define cpu_exec cpu_ppc_exec -#define cpu_gen_code cpu_ppc_gen_code #define cpu_signal_handler cpu_ppc_signal_handler #define cpu_list ppc_cpu_list diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 68d6528..95015d5 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -599,7 +599,6 @@ bool css_present(uint8_t cssid); #define cpu_init(model) CPU(cpu_s390x_init(model)) #define cpu_exec cpu_s390x_exec -#define cpu_gen_code cpu_s390x_gen_code #define cpu_signal_handler cpu_s390x_signal_handler void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf); diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index ea854cb..8d44ce7 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -228,7 +228,6 @@ void cpu_load_tlb(CPUSH4State * env); #define cpu_init(cpu_model) CPU(cpu_sh4_init(cpu_model)) #define cpu_exec cpu_sh4_exec -#define cpu_gen_code cpu_sh4_gen_code #define cpu_signal_handler cpu_sh4_signal_handler #define cpu_list sh4_cpu_list diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index ac8f383..f24e9c4 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -599,7 +599,6 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); #endif #define cpu_exec cpu_sparc_exec -#define cpu_gen_code cpu_sparc_gen_code #define cpu_signal_handler cpu_sparc_signal_handler #define cpu_list sparc_cpu_list diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h index b9f5082..bcc1fdb 100644 --- a/target-tilegx/cpu.h +++ b/target-tilegx/cpu.h @@ -163,7 +163,6 @@ TileGXCPU *cpu_tilegx_init(const char *cpu_model); #define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model)) #define cpu_exec cpu_tilegx_exec -#define cpu_gen_code cpu_tilegx_gen_code #define cpu_signal_handler cpu_tilegx_signal_handler static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc, diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index dbd2c9c..c692470 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -383,7 +383,6 @@ typedef struct CPUXtensaState { #include "cpu-qom.h" #define cpu_exec cpu_xtensa_exec -#define cpu_gen_code cpu_xtensa_gen_code #define cpu_signal_handler cpu_xtensa_signal_handler #define cpu_list xtensa_cpu_list